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Searched refs:sosccsr (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/mx7ulp/
A Dscg.c24 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
152 reg = readl(&scg1_regs->sosccsr); in scg_soscdiv_get_rate()
1007 while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) in scg_a7_soscdiv_init()
1054 if ((readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) { in scg_a7_init_core_clk()
/u-boot/arch/arm/include/asm/arch-mx7ulp/
A Dscg.h270 u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */ member

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