| /u-boot/board/ti/ks2_evm/ |
| A D | board_k2e.c | 52 int speeds[DEVSPEED_NUMSPDS] = { variable
81 speed = get_max_dev_speed(speeds); in get_pll_init_data()
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| A D | board_k2l.c | 72 speed = get_max_dev_speed(speeds); in get_pll_init_data()
76 speed = get_max_arm_speed(speeds); in get_pll_init_data()
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| A D | board_k2hk.c | 84 speed = get_max_dev_speed(speeds); in get_pll_init_data()
88 speed = get_max_arm_speed(speeds); in get_pll_init_data()
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| A D | board_k2g.c | 64 int speeds[DEVSPEED_NUMSPDS] = { variable
194 speed = get_max_arm_speed(speeds); in get_pll_init_data()
205 speed = get_max_arm_speed(speeds); in get_pll_init_data()
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| /u-boot/drivers/i2c/ |
| A D | designware_i2c_pci.c | 149 u32 speeds[4]; in dw_i2c_acpi_fill_ssdt() local
167 if (size > ARRAY_SIZE(speeds)) in dw_i2c_acpi_fill_ssdt()
170 ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size); in dw_i2c_acpi_fill_ssdt()
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| /u-boot/arch/arm/mach-keystone/include/mach/ |
| A D | clock.h | 121 extern int speeds[];
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| /u-boot/arch/arm/mach-keystone/ |
| A D | init.c | 238 int speed = get_max_arm_speed(speeds); in print_cpuinfo()
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| A D | clock.c | 15 int __weak speeds[DEVSPEED_NUMSPDS] = { variable
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| /u-boot/drivers/phy/marvell/ |
| A D | comphy_cp110.c | 36 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
37 (((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
39 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
41 ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds))
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | README | 26 extracted from DDR chip datasheet. Different speeds of DDR are supported with
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| /u-boot/board/intel/ |
| A D | Kconfig | 59 architecture (ISA) compatible, operating at speeds up to 400Mhz,
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| /u-boot/drivers/usb/ |
| A D | Kconfig | 5 subsystem which offers higher speeds and more features than the
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| /u-boot/arch/x86/dts/ |
| A D | chromebook_coral.dts | 383 i2c,speeds = <100000 400000 1000000>;
417 i2c,speeds = <100000 400000 1000000 3400000>;
430 i2c,speeds = <100000 400000 1000000>;
457 i2c,speeds = <100000 400000>;
499 i2c,speeds = <100000 400000>;
533 i2c,speeds = <100000 400000 1000000>;
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| /u-boot/board/freescale/ls1021atwr/ |
| A D | README | 37 supporting speeds up to 1600Mtps
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| /u-boot/board/freescale/ls1021aqds/ |
| A D | README | 37 supporting speeds up to 1600Mtps
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| /u-boot/doc/board/kontron/ |
| A D | sl28.rst | 132 The board is prepared to supply different SerDes clock speeds. But for now,
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| /u-boot/doc/ |
| A D | README.falcon | 207 clocks speeds etc. To generate this patched DT blob, you can use
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| /u-boot/doc/board/google/ |
| A D | chromebook_coral.rst | 85 SPL uses SPI flash to update the MRC caches in ROM. This speeds up subsequent
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | Kconfig | 530 clock speeds.
546 clocks speeds (up to 600MHz). If unsure, keep as 0.
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| /u-boot/doc/driver-model/ |
| A D | usb-info.rst | 141 Up to 127 devices can be on each bus. USB has four bus speeds: low
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| /u-boot/doc/arch/ |
| A D | x86.rst | 474 limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
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| /u-boot/tools/buildman/ |
| A D | README | 963 hence speeds up the build. To force use of 'make mrproper', use -the -m flag.
|