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Searched refs:spll_pdiv (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-exynos/
A Dclock_init.h75 unsigned spll_pdiv; member
A Dclock_init_exynos5.c177 .spll_pdiv = 0x3,
802 writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); in exynos5420_system_clock_init()
898 val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv); in exynos5420_system_clock_init()

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