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Searched refs:spllcfg (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/mx7ulp/
A Dscg.c300 reg = readl(&scg1_regs->spllcfg); in scg_spll_get_rate()
495 reg = readl(&scg1_regs->spllcfg); in decode_pll()
892 writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg); in scg_a7_spll_init()
1061 val = readl(&scg1_regs->spllcfg); in scg_a7_init_core_clk()
1063 writel(val, &scg1_regs->spllcfg); in scg_a7_init_core_clk()
1072 val = readl(&scg1_regs->spllcfg); in scg_a7_init_core_clk()
1074 writel(val, &scg1_regs->spllcfg); in scg_a7_init_core_clk()
/u-boot/arch/arm/include/asm/arch-mx7ulp/
A Dscg.h310 u32 spllcfg; /* System PLL Configuration Register */ member

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