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Searched refs:sr (Results 1 – 25 of 167) sorted by relevance

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/u-boot/arch/m68k/lib/
A Dinterrupts.c31 unsigned short sr; in get_sr() local
33 asm volatile ("move.w %%sr,%0":"=r" (sr):); in get_sr()
35 return sr; in get_sr()
38 static __inline__ void set_sr (unsigned short sr) in set_sr() argument
40 asm volatile ("move.w %0,%%sr"::"r" (sr)); in set_sr()
71 unsigned short sr; in enable_interrupts() local
73 sr = get_sr (); in enable_interrupts()
74 set_sr (sr & ~0x0700); in enable_interrupts()
79 unsigned short sr; in disable_interrupts() local
81 sr = get_sr (); in disable_interrupts()
[all …]
/u-boot/arch/xtensa/include/asm/arch-de212/
A Dtie.h69 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
70 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
71 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
72 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
73 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
74 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
75 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
/u-boot/arch/xtensa/include/asm/arch-dc233c/
A Dtie.h93 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
94 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
95 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
99 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
/u-boot/arch/xtensa/include/asm/arch-dc232b/
A Dtie.h92 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
93 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
95 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
/u-boot/drivers/spi/
A Dstm32_spi.c153 ((sr & SPI_SR_RXP) || in stm32_spi_read_rxfifo()
154 ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) { in stm32_spi_read_rxfifo()
230 u32 cr1, sr; in stm32_spi_stopxfer() local
247 sr, !(sr & SPI_SR_SUSP), in stm32_spi_stopxfer()
370 u32 sr; in stm32_spi_xfer() local
426 if (sr & SPI_SR_OVR) { in stm32_spi_xfer()
432 if (sr & SPI_SR_SUSP) { in stm32_spi_xfer()
441 if (sr & SPI_SR_TXTF) in stm32_spi_xfer()
444 if (sr & SPI_SR_TXP) in stm32_spi_xfer()
448 if (sr & SPI_SR_RXP) in stm32_spi_xfer()
[all …]
A Dstm32_qspi.c30 u32 sr; /* 0x08 */ member
135 u32 sr; in _stm32_qspi_wait_for_not_busy() local
138 ret = readl_poll_timeout(&priv->regs->sr, sr, in _stm32_qspi_wait_for_not_busy()
139 !(sr & STM32_QSPI_SR_BUSY), in _stm32_qspi_wait_for_not_busy()
150 u32 sr; in _stm32_qspi_wait_cmd() local
156 ret = readl_poll_timeout(&priv->regs->sr, sr, in _stm32_qspi_wait_cmd()
157 sr & STM32_QSPI_SR_TCF, in _stm32_qspi_wait_cmd()
160 log_err("cmd timeout (stat:%#x)\n", sr); in _stm32_qspi_wait_cmd()
187 u32 len = op->data.nbytes, sr; in _stm32_qspi_poll() local
201 ret = readl_poll_timeout(&priv->regs->sr, sr, in _stm32_qspi_poll()
[all …]
/u-boot/arch/arc/lib/
A Dstart.S13 sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
45 sr r5, [ARC_AUX_DC_CTRL]
48 sr r5, [ARC_AUX_DC_IVDC]
135 sr %r0, [ARC_AUX_INTR_VEC_BASE]
/u-boot/arch/arm/mach-at91/
A Dspl_at91.c38 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { in lowlevel_clock_init()
43 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) in lowlevel_clock_init()
55 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in lowlevel_clock_init()
61 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in lowlevel_clock_init()
/u-boot/arch/arm/mach-at91/arm926ejs/
A Dclock.c208 while (!(readl(&pmc->sr) & AT91_PMC_LOCKA)) in at91_plla_init()
216 while (!(readl(&pmc->sr) & AT91_PMC_LOCKB)) in at91_pllb_init()
229 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init()
236 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init()
243 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init()
250 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init()
261 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) { in at91_pllb_clk_enable()
279 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) { in at91_pllb_clk_disable()
/u-boot/arch/m68k/cpu/mcf547x_8x/
A Dslicetimer.c48 setbits_be32(&timerp->sr, SLT_SR_ST); in __udelay()
58 setbits_be32(&timerp->sr, SLT_SR_ST); in dtimer_interrupt()
74 out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST); in timer_init()
/u-boot/drivers/rtc/
A Drv3029.c219 u8 sr; in rv3029_eeprom_busywait() local
222 ret = rv3029_get_sr(dev, &sr); in rv3029_eeprom_busywait()
225 if (!(sr & RV3029_STATUS_EEBUSY)) in rv3029_eeprom_busywait()
268 u8 sr; in rv3029_eeprom_enter() local
271 ret = rv3029_get_sr(dev, &sr); in rv3029_eeprom_enter()
274 if (sr & (RV3029_STATUS_VLOW1 | RV3029_STATUS_VLOW2)) { in rv3029_eeprom_enter()
278 sr &= ~RV3029_STATUS_VLOW1; in rv3029_eeprom_enter()
279 sr &= ~RV3029_STATUS_VLOW2; in rv3029_eeprom_enter()
280 ret = rv3029_set_sr(dev, sr); in rv3029_eeprom_enter()
284 ret = rv3029_get_sr(dev, &sr); in rv3029_eeprom_enter()
[all …]
/u-boot/arch/m68k/include/asm/
A Dptrace.h31 unsigned short sr; member
34 unsigned short sr; member
/u-boot/arch/m68k/cpu/mcf52x2/
A Dcpu.c63 out_be16(&wdt->sr, 0x5555); in watchdog_reset()
64 out_be16(&wdt->sr, 0xaaaa); in watchdog_reset()
72 out_be16(&wdt->sr, 0x5555); in watchdog_disable()
73 out_be16(&wdt->sr, 0xaaaa); in watchdog_disable()
93 out_be16(&wdt->sr, 0x5555); in watchdog_init()
94 out_be16(&wdt->sr, 0xaaaa); in watchdog_init()
/u-boot/drivers/rng/
A Dstm32mp1_rng.c42 u32 sr, count, reg; in stm32_rng_read() local
47 retval = readl_poll_timeout(pdata->base + RNG_SR, sr, in stm32_rng_read()
48 sr & RNG_SR_DRDY, 10000); in stm32_rng_read()
52 if (sr & (RNG_SR_SEIS | RNG_SR_SECS)) { in stm32_rng_read()
/u-boot/drivers/mtd/
A Dstm32_flash.c98 while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) in flash_erase()
117 while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) in flash_erase()
131 while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) in write_buff()
144 while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) in write_buff()
A Dst_smi.c209 int sr; in smi_wait_till_ready() local
215 sr = smi_read_sr(bank); in smi_wait_till_ready()
216 if ((sr >= 0) && (!(sr & WIP_BIT))) in smi_wait_till_ready()
239 int sr; in smi_write_enable() local
258 sr = smi_read_sr(bank); in smi_write_enable()
259 if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT)))) in smi_write_enable()
/u-boot/drivers/i2c/
A Dat91_i2c.c30 u32 sr; in at91_wait_for_xfer() local
35 sr = readl(&reg->sr); in at91_wait_for_xfer()
36 bus->status |= sr; in at91_wait_for_xfer()
38 if (sr & TWI_SR_NACK) in at91_wait_for_xfer()
40 else if (sr & status) in at91_wait_for_xfer()
58 readl(&reg->sr); in at91_i2c_xfer_msg()
A Dfsl_i2c.c234 while (!(readb(&base->sr) & I2C_SR_MBB)) { in fsl_i2c_fixup()
239 if (readb(&base->sr) & I2C_SR_MAL) { in fsl_i2c_fixup()
250 while (!(readb(&base->sr) & I2C_SR_MIF)) { in fsl_i2c_fixup()
258 writeb(0, &base->sr); in fsl_i2c_fixup()
281 writeb(0x0, &base->sr); /* clear status register */ in __i2c_init()
285 while (readb(&base->sr) & I2C_SR_MBB) { in __i2c_init()
302 while (readb(&base->sr) & I2C_SR_MBB) { in i2c_wait4bus()
317 csr = readb(&base->sr); in i2c_wait()
321 csr = readb(&base->sr); in i2c_wait()
323 writeb(0x0, &base->sr); in i2c_wait()
/u-boot/arch/sh/include/asm/
A Dptrace.h56 unsigned long sr; member
88 #define user_mode(regs) (((regs)->sr & 0x40000000)==0)
/u-boot/arch/m68k/cpu/mcf523x/
A Dcpu.c72 out_be16(&wdp->sr, 0x5555); in watchdog_reset()
74 out_be16(&wdp->sr, 0xaaaa); in watchdog_reset()
/u-boot/arch/m68k/cpu/mcf532x/
A Dcpu.c112 out_be16(&wdp->sr, 0x5555); in watchdog_reset()
113 out_be16(&wdp->sr, 0xaaaa); in watchdog_reset()
/u-boot/arch/powerpc/include/asm/
A Dfsl_dma.h31 uint sr; /* DMA status register */ member
70 uint sr; /* DMA status register */ member
/u-boot/arch/arm/mach-at91/armv7/
A Dclock.c122 while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) in at91_plla_init()
150 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init()
170 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init_down()
250 status = readl(&pmc->sr); in at91_enable_periph_generated_clk()
/u-boot/arch/arm/mach-at91/include/mach/
A Dat91_rtt.h19 u32 sr; /* Status Register RO 0x00000000 */ member
/u-boot/drivers/mtd/spi/
A Dspi-nor-tiny.c298 int sr = read_sr(nor); in spi_nor_sr_ready() local
300 if (sr < 0) in spi_nor_sr_ready()
301 return sr; in spi_nor_sr_ready()
303 return !(sr & SR_WIP); in spi_nor_sr_ready()
317 int sr, fsr; in spi_nor_ready() local
319 sr = spi_nor_sr_ready(nor); in spi_nor_ready()
320 if (sr < 0) in spi_nor_ready()
321 return sr; in spi_nor_ready()
325 return sr && fsr; in spi_nor_ready()

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