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/u-boot/arch/arm/mach-bcmstb/
A DKconfig8 is acting as the second stage bootloader, and U-Boot is
9 acting as the third stage bootloader (TSBL), loaded by BOLT.
16 is acting as the second stage bootloader, and U-Boot is
17 acting as the third stage bootloader (TSBL), loaded by BOLT.
36 hex "Address to which the prior stage provided DTB will be copied"
/u-boot/tools/binman/test/
A D104_cbfs_stage.dts14 filename = "cbfs-stage.elf";
15 cbfs-type = "stage";
/u-boot/cmd/
A Dsf.c405 int stage; member
411 static void show_time(struct test_info *test, int stage) in show_time() argument
417 if (test->time_ms[stage]) in show_time()
418 do_div(speed, test->time_ms[stage] * 1024); in show_time()
421 printf("%d %s: %u ticks, %d KiB/s %d.%03d Mbps\n", stage, in show_time()
422 stage_name[stage], test->time_ms[stage], in show_time()
428 test->time_ms[test->stage] = get_timer(test->base_ms); in spi_test_next_stage()
429 show_time(test, test->stage); in spi_test_next_stage()
431 test->stage++; in spi_test_next_stage()
A Dbcb.c102 *fieldp = bcb.stage; in bcb_field_get()
103 *sizep = sizeof(bcb.stage); in bcb_field_get()
/u-boot/doc/board/google/
A Dchromebook_samus.rst52 fallback/romstage 0x722a00 stage 54210
53 fallback/ramstage 0x72fe00 stage 96382
55 fallback/vboot 0x748ec0 stage 15980
56 fallback/refcode 0x74cd80 stage 75578
72 and decompresses the stage to produce a coreboot rmodule. This is a simple
73 representation of an ELF file. You need the patch "Support decoding a stage
/u-boot/board/vamrs/rock960_rk3399/
A DREADME123 The idbspl.img contains the first stage, and the u-boot.img the second stage.
124 As explained in the Rockchip partition table reference [1], the first stage
125 (aka loader1) start sector is 64, and the second stage start sector is 16384.
127 Each sector is 512 bytes, which means the first stage offset is 32 KiB,
128 and the second stage offset is 8 MiB.
130 Note: the second stage location is actually not as per the spec,
132 stage.
/u-boot/
A D.gitlab-ci.yml15 stage: test.py
57 stage: world build
68 stage: world build
106 stage: testsuites
113 stage: testsuites
123 stage: testsuites
133 stage: testsuites
140 stage: testsuites
147 stage: testsuites
154 stage: testsuites
[all …]
/u-boot/doc/uImage.FIT/
A Dverified-boot.txt76 1. Master private key is used by the signer to sign a first-stage image.
78 2. Secondary private key is created and used to sign second-stage images.
79 3. Secondary public key is placed in first stage images
80 4. We use the master public key to verify the first-stage image. We then
81 use the secondary public key in the first-stage image to verify the second-
84 different key at each stage, so that a compromise in one place will not
/u-boot/drivers/clk/
A Dclk-uclass.c209 static int clk_set_default_parents(struct udevice *dev, int stage) in clk_set_default_parents() argument
253 if (stage == 0 && clk.dev == dev) in clk_set_default_parents()
256 if (stage > 0 && clk.dev != dev) in clk_set_default_parents()
282 static int clk_set_default_rates(struct udevice *dev, int stage) in clk_set_default_rates() argument
321 if (stage == 0 && clk.dev == dev) in clk_set_default_rates()
324 if (stage > 0 && clk.dev != dev) in clk_set_default_rates()
346 int clk_set_defaults(struct udevice *dev, int stage) in clk_set_defaults() argument
359 ret = clk_set_default_parents(dev, stage); in clk_set_defaults()
363 ret = clk_set_default_rates(dev, stage); in clk_set_defaults()
/u-boot/lib/zstd/
A Ddecompress.c81 ZSTD_dStage stage; member
1716 switch (dctx->stage) { in ZSTD_nextInputType()
1742 switch (dctx->stage) { in ZSTD_decompressContinue()
2155 ZSTD_dStreamStage stage; member
2199 zds->stage = zdss_init; in ZSTD_createDStream_advanced()
2299 switch (zds->stage) { in ZSTD_decompressStream()
2334 zds->stage = zdss_init; in ZSTD_decompressStream()
2367 zds->stage = zdss_read; in ZSTD_decompressStream()
2374 zds->stage = zdss_init; in ZSTD_decompressStream()
2395 zds->stage = zdss_load; in ZSTD_decompressStream()
[all …]
/u-boot/include/
A Dclk.h292 int clk_set_defaults(struct udevice *dev, int stage);
294 static inline int clk_set_defaults(struct udevice *dev, int stage) in clk_set_defaults() argument
A Dandroid_bootloader_message.h75 char stage[32]; member
/u-boot/doc/device-tree-bindings/
A Dchosen.txt78 In a system using an SPL stage and having multiple boot sources
111 will be injected automatically by the SPL stage to notify a later stage
112 of where said later stage was booted from.
/u-boot/doc/SPL/
A DREADME.spl-secure-boot13 The SPL image is responsible for loading the next stage boot loader, which is
/u-boot/arch/arm/dts/
A Dimx6q-display5-u-boot.dtsi11 * configuration in the pre-relocation stage of U-Boot
/u-boot/arch/arm/mach-rockchip/
A DKconfig344 first stage in segments and enter multiple times. E.g. on
345 the RK3188, the first 1KB of the first stage are loaded
347 remainder of the first stage is loaded, but the BROM
350 This enables support code in the BOOT0 hook for the SPL stage
358 first stage in segments and enter multiple times. E.g. on
359 the RK3188, the first 1KB of the first stage are loaded
361 remainder of the first stage is loaded, but the BROM
364 This enables support code in the BOOT0 hook for the TPL stage
/u-boot/tools/buildman/
A Dfunc_test.py384 def _HandleMake(self, commit, brd, stage, cwd, *args, **kwargs): argument
396 if stage == 'mrproper':
398 elif stage == 'config':
401 elif stage == 'build':
416 print('make', stage)
/u-boot/arch/arm/mach-stm32mp/
A DKconfig97 hex "Size of the DDR marked cacheable in pre-reloc stage"
102 pre-reloc stage.
/u-boot/doc/
A DREADME.multi-dtb-fit31 The compression stage is optional but reduces the impact on the size of the
39 during the early initialization stage of the SPL (spl_early_init() or
A DREADME.bloblist66 bloblist in preparation for the next stage. This involves adding a checksum so
67 that the next stage can make sure that the data arrived safely. While the
A DREADME.mediatek56 - BootROM image header. This header is used by the first stage bootloader. It records
87 For first stage bootloader like U-Boot SPL or preloader, it usually points to the
90 For second stage bootloader like U-Boot, it usually points to the DRAM.
/u-boot/arch/mips/mach-mtmips/mt7628/
A DKconfig41 bool "Use alternative pinmux for UART2 in SPL stage"
/u-boot/common/spl/
A DKconfig150 string "Linker script for the SPL stage"
155 U-Boot stage. Set this to the path of the linker-script to
181 from the SPL stage.
1366 loading of U-Boot's SPL stage. If unsure, say Y.
1393 string "Linker script for the TPL stage"
1404 fall back to the linker-script used for the SPL stage.
1413 .text sections of the TPL stage has to be set below.
1421 stack-pointer from the settings for the SPL stage.
1430 int "Maximum size (in bytes) for the TPL stage"
1434 The maximum size (in bytes) of the TPL stage.
[all …]
/u-boot/board/qualcomm/dragonboard410c/
A Dreadme.txt46 Later on proper device tree is passed to next boot stage.
/u-boot/board/theobroma-systems/lion_rk3368/
A DREADME17 Build the TPL/SPL stage

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