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Searched refs:stv0991_cgu_regs (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/cpu/armv7/stv0991/
A Dclock.c12 static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ variable
13 (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
18 writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01), in enable_pll1()
19 &stv0991_cgu_regs->pll1_ctrl); in enable_pll1()
26 writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq); in clock_setup()
30 writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq); in clock_setup()
33 writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK) in clock_setup()
34 | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl); in clock_setup()
37 writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq); in clock_setup()
A Dtimer.c17 static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ variable
18 (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
33 writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq); in timer_init()
34 writel(readl(&stv0991_cgu_regs->cgu_enable_2) | in timer_init()
35 TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2); in timer_init()
/u-boot/arch/arm/include/asm/arch-stv0991/
A Dstv0991_cgu.h10 struct stv0991_cgu_regs { struct

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