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Searched refs:sw (Results 1 – 25 of 66) sorted by relevance

123

/u-boot/board/imgtec/malta/
A Dlowlevel_init.S67 sw t0, GT_ISD_OFS(t1)
74 sw t0, GT_PCI0IOLD_OFS(t1)
76 sw t0, GT_PCI0IOHD_OFS(t1)
80 sw t0, GT_PCI0M0LD_OFS(t1)
82 sw t0, GT_PCI0M0HD_OFS(t1)
85 sw t0, GT_PCI0M1LD_OFS(t1)
87 sw t0, GT_PCI0M1HD_OFS(t1)
109 sw t1, MSC01_PBC_CS0RW_OFS(t0)
172 sw t1, MSC01_PCI_BAR0_OFS(t0)
217 sw t1, MSC01_PCI_SWAP_OFS(t0)
[all …]
/u-boot/board/freescale/common/
A Dmc34vr500.c21 int mc34vr500_get_sw_volt(uint8_t sw) in mc34vr500_get_sw_volt() argument
30 __func__, sw + 1, swxvolt_addr[sw]); in mc34vr500_get_sw_volt()
31 if (sw > SW4) { in mc34vr500_get_sw_volt()
32 printf("%s: Unsupported SW(sw%d)\n", __func__, sw + 1); in mc34vr500_get_sw_volt()
46 ret = pmic_reg_read(p, swxvolt_addr[sw], &swxvolt); in mc34vr500_get_sw_volt()
48 printf("%s: Failed to get SW%u volt\n", __func__, sw + 1); in mc34vr500_get_sw_volt()
53 spb = swx_set_point_base[sw]; in mc34vr500_get_sw_volt()
61 int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt) in mc34vr500_set_sw_volt() argument
70 if (sw > SW4 || sw_volt < 625) in mc34vr500_set_sw_volt()
83 spb = swx_set_point_base[sw]; in mc34vr500_set_sw_volt()
[all …]
/u-boot/board/freescale/corenet_ds/
A Dcorenet_ds.c31 u8 sw; in checkboard() local
44 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; in checkboard()
46 if (sw < 0x8) in checkboard()
47 printf("vBank: %d\n", sw); in checkboard()
48 else if (sw == 0x8) in checkboard()
50 else if (sw == 0x9) in checkboard()
65 sw = in_8(&PIXIS_SW(5)); in checkboard()
73 sw = in_8(&PIXIS_SW(9)); in checkboard()
78 sw = in_8(&PIXIS_SW(3)); in checkboard()
141 u8 sw; in misc_init_r() local
[all …]
/u-boot/arch/mips/mach-ath79/qca956x/
A Dqca956x-ddr-tap.S30 sw a1, 0x1c(a0)
57 sw t3, 0x1c(t0) /* TAP_CONTROL_0_ADDRESS */
58 sw t3, 0x20(t0) /* TAP_CONTROL_1_ADDRESS */
59 sw t3, 0x24(t0) /* TAP_CONTROL_2_ADDRESS */
60 sw t3, 0x28(t0) /* TAP_CONTROL_3_ADDRESS */
93 sw t1, 0x011c(t0) /* DDR_BIST_ADDRESS */
127 sw t1, 0x4(t0)
138 sw t1, 0x4(t0)
147 sw t1, 0x0(t0)
148 sw t1, 0x4(t0)
[all …]
/u-boot/board/freescale/ls2080aqds/
A Dls2080aqds.c66 u8 sw; in checkboard() local
74 sw = QIXIS_READ(arch); in checkboard()
81 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; in checkboard()
83 if (sw < 0x8) in checkboard()
85 else if (sw == 0x8) in checkboard()
87 else if (sw == 0x9) in checkboard()
89 else if (sw == 0xf) in checkboard()
91 else if (sw == 0x15) in checkboard()
112 clock = (sw >> 6) & 3; in checkboard()
114 clock = (sw >> 4) & 3; in checkboard()
[all …]
/u-boot/board/freescale/ls1028a/
A Dls1028a.c255 u8 sw; in checkboard() local
265 sw = QIXIS_READ(id); in checkboard()
267 switch (sw) { in checkboard()
282 sw = QIXIS_READ(arch); in checkboard()
286 sw = QIXIS_READ(brdcfg[0]); in checkboard()
287 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; in checkboard()
301 switch (sw) { in checkboard()
323 clock = (sw >> 6) & 3; in checkboard()
325 clock = (sw >> 4) & 0xf; in checkboard()
330 clock = (sw >> 4) & 3; in checkboard()
[all …]
/u-boot/board/freescale/t208xqds/
A Dt208xqds.c37 u8 sw; in checkboard() local
45 sw = QIXIS_READ(arch); in checkboard()
54 sw = QIXIS_READ(brdcfg[0]); in checkboard()
55 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; in checkboard()
57 if (sw < 0x8) in checkboard()
58 printf("vBank%d\n", sw); in checkboard()
59 else if (sw == 0x8) in checkboard()
61 else if (sw == 0x9) in checkboard()
73 sw = QIXIS_READ(brdcfg[2]); in checkboard()
75 freq[(sw >> 4) & 0x3]); in checkboard()
[all …]
/u-boot/board/freescale/t4rdb/
A Dt4240rdb.c34 u8 sw; in checkboard() local
40 sw = CPLD_READ(vbank); in checkboard()
41 sw = sw & CPLD_BANK_SEL_MASK; in checkboard()
43 if (sw <= 7) in checkboard()
44 printf("vBank: %d\n", sw); in checkboard()
46 printf("Unsupported Bank=%x\n", sw); in checkboard()
/u-boot/arch/mips/mach-ath79/qca953x/
A Dlowlevel_init.S116 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
129 sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
131 sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
132 sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
137 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
141 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
145 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
149 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
155 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
167 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
[all …]
/u-boot/arch/mips/mach-ath79/ar933x/
A Dlowlevel_init.S106 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
112 sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
118 sw t1, AR933X_RTC_REG_RESET(t0)
123 sw t1, AR933X_RTC_REG_RESET(t0)
145 sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
153 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
159 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
172 sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
186 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
210 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
[all …]
/u-boot/board/freescale/ls2080ardb/
A Dls2080ardb.c109 u8 sw; in checkboard() local
118 sw = QIXIS_READ(arch); in checkboard()
122 sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK; in checkboard()
123 switch (sw) { in checkboard()
155 sw = QIXIS_READ(arch); in checkboard()
160 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; in checkboard()
162 if (sw < 0x8) in checkboard()
164 else if (sw == 0x9) in checkboard()
555 u8 sw; in update_spd_address() local
557 sw = QIXIS_READ(arch); in update_spd_address()
[all …]
/u-boot/arch/mips/mach-mscc/
A Dlowlevel_init_luton.S31 sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
34 sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
37 sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
40 sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
59 sw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
/u-boot/board/freescale/p2041rdb/
A Dp2041rdb.c32 u8 sw; in checkboard() local
40 sw = CPLD_READ(fbank_sel); in checkboard()
41 printf("vBank: %d\n", sw & 0x1); in checkboard()
52 sw = in_8(&CPLD_SW(2)) >> 2; in checkboard()
57 unsigned int clock = (sw >> (2 * i)) & 3; in checkboard()
172 u8 sw; in misc_init_r() local
179 sw = in_8(&CPLD_SW(2)) >> 2; in misc_init_r()
181 unsigned int clock = (sw >> (2 * i)) & 3; in misc_init_r()
A Dcpld.h27 u8 sw[1]; /* 0xd - SW2 Status */ member
48 #define CPLD_SW(x) (cpld->sw[(x) - 2])
/u-boot/board/freescale/t104xrdb/
A Dt104xrdb.c35 u8 sw; in checkboard() local
45 sw = CPLD_READ(flash_ctl_status); in checkboard()
46 sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); in checkboard()
48 printf("vBank: %d\n", sw); in checkboard()
A Ddiu.c69 u8 sw; in platform_diu_init() local
72 sw = CPLD_READ(sfp_ctl_status); in platform_diu_init()
73 CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP)); in platform_diu_init()
/u-boot/arch/arm/include/asm/arch-omap3/
A Ddss.h218 #define DSS_HSW(sw) ((sw) - 1) argument
221 #define DSS_VSW(sw) ((sw) - 1) argument
223 #define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw)) argument
224 #define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw)) argument
/u-boot/board/freescale/ls1088a/
A Dls1088a.c256 u8 sw; in checkboard() local
270 sw = QIXIS_READ(arch); in checkboard()
282 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; in checkboard()
292 switch (sw) { in checkboard()
316 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; in checkboard()
317 if (sw == 0 || sw == 4) in checkboard()
319 else if (sw == 1) in checkboard()
350 clock = (sw >> 6) & 3; in checkboard()
352 clock = (sw >> 4) & 3; in checkboard()
356 clock = (sw >> 2) & 3; in checkboard()
[all …]
/u-boot/board/freescale/ls1021aqds/
A Dls1021aqds.c67 u8 sw; in checkboard() local
77 sw = QIXIS_READ(brdcfg[0]); in checkboard()
78 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; in checkboard()
80 if (sw < 0x8) in checkboard()
81 printf("vBank: %d\n", sw); in checkboard()
82 else if (sw == 0x8) in checkboard()
84 else if (sw == 0x9) in checkboard()
86 else if (sw == 0x15) in checkboard()
/u-boot/board/freescale/lx2160a/
A Dlx2160a.c301 u8 sw; in checkboard() local
317 sw = QIXIS_READ(arch); in checkboard()
326 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; in checkboard()
327 switch (sw) { in checkboard()
358 sw = QIXIS_READ(brdcfg[2]); in checkboard()
359 clock = sw >> 4; in checkboard()
362 clock = sw & 0x0f; in checkboard()
365 sw = QIXIS_READ(brdcfg[3]); in checkboard()
367 clock = sw >> 4; in checkboard()
369 clock = sw & 0x0f; in checkboard()
[all …]
/u-boot/board/freescale/ls1046aqds/
A Dls1046aqds.c179 u8 sw; in checkboard() local
193 sw = QIXIS_READ(brdcfg[0]); in checkboard()
194 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; in checkboard()
196 if (sw < 0x8) in checkboard()
197 printf("vBank: %d\n", sw); in checkboard()
198 else if (sw == 0x8) in checkboard()
200 else if (sw == 0x9) in checkboard()
202 else if (sw == 0xF) in checkboard()
/u-boot/board/freescale/ls1012aqds/
A Dls1012aqds.c41 u8 sw; in checkboard() local
43 sw = QIXIS_READ(arch); in checkboard()
44 printf("Board Arch: V%d, ", sw >> 4); in checkboard()
45 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); in checkboard()
47 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); in checkboard()
49 if (sw & QIXIS_LBMAP_ALTBANK) in checkboard()
/u-boot/board/freescale/ls1043aqds/
A Dls1043aqds.c189 u8 sw; in checkboard() local
203 sw = QIXIS_READ(brdcfg[0]); in checkboard()
204 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; in checkboard()
206 if (sw < 0x8) in checkboard()
207 printf("vBank: %d\n", sw); in checkboard()
208 else if (sw == 0x8) in checkboard()
210 else if (sw == 0x9) in checkboard()
212 else if (sw == 0xF) in checkboard()
/u-boot/arch/mips/cpu/
A Dcm_init.S37 sw zero, GCR_BASE_UPPER(t0)
38 sw t1, GCR_BASE(t0)
/u-boot/board/imgtec/boston/
A Dlowlevel_init.S48 sw k1, 0(AT)
50 sw k1, 4(AT)

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