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Searched refs:sys_pll_psc (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/clk/
A Dclk_stm32f.c108 .sys_pll_psc = {
122 .sys_pll_psc = {
152 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; in configure_clocks() local
169 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT) in configure_clocks()
170 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT) in configure_clocks()
171 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT))); in configure_clocks()
176 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT); in configure_clocks()
178 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT); in configure_clocks()
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
182 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT); in configure_clocks()
[all …]
A Dclk_stm32h7.c337 struct pll_psc sys_pll_psc = { variable
399 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; in configure_clocks()
402 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT; in configure_clocks()
403 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT; in configure_clocks()
404 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; in configure_clocks()
405 pll1divr |= (sys_pll_psc.divn - 1); in configure_clocks()
/u-boot/include/
A Dstm32_rcc.h37 struct pll_psc sys_pll_psc; member

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