Searched refs:t5 (Results 1 – 8 of 8) sorted by relevance
| /u-boot/arch/riscv/cpu/ |
| A D | start.S | 194 la t5, board_init_f
285 LREG t5, 0(t0)
287 SREG t5, 0(t1)
312 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
314 SREG t5, 0(t3)
324 andi t5, t5, 0xFF /* t5 <--- relocation type */
329 li t5, SYM_SIZE
330 mul t0, t0, t5
334 add t5, t5, t0
335 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
[all …]
|
| /u-boot/arch/mips/mach-ath79/ar933x/ |
| A D | lowlevel_init.S | 100 lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
101 andi t1, t5, 0x10
136 andi t1, t5, 0x01 # t5 BOOT_STRAP
163 andi t1, t5, 0x01 # t5 BOOT_STRAP
177 andi t1, t5, 0x01 # t5 BOOT_STRAP
201 andi t1, t5, 0x01 # t5 BOOT_STRAP
|
| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | qca956x-ddr-tap.S | 108 li t5, 0x00000000
109 sw t5, 0x011c(t0) /* DDR_BIST_ADDRESS - Stop the DDR BIST test */
111 li t5, 0x0001fe00
112 and t5, t5, t1
113 bnez t5, _iterate_tap /* This is a redundant compare but nevertheless - Comparing the FAILS */
|
| /u-boot/arch/mips/include/asm/ |
| A D | regdef.h | 33 #define t5 $13 macro
|
| /u-boot/arch/nds32/cpu/n1213/ |
| A D | start.S | 333 sll $t5, $t4, $t1 ! get $t5 cache line size
342 sub $p1, $p1, $t5
368 sll $t5, $t4, $t1 ! get $t5 cache line size
377 sub $p1, $p1, $t5
|
| /u-boot/arch/riscv/include/asm/ |
| A D | ptrace.h | 43 unsigned long t5; member
|
| /u-boot/arch/riscv/lib/ |
| A D | interrupts.c | 50 regs->t4, regs->t5, regs->t6); in show_regs()
|
| /u-boot/drivers/mtd/nand/raw/ |
| A D | octeontx_nand.c | 351 t1, t2, t3, t4, t5, t6, t7, /* settable per ONFI-timing mode */ enumerator
858 cmd.u.ale_cmd.alen3 = t5; in ndf_queue_cmd_ale()
|
Completed in 12 milliseconds