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Searched refs:tRCD (Results 1 – 13 of 13) sorted by relevance

/u-boot/arch/arm/mach-omap2/omap4/
A Demif.c27 .tRCD = 18,
51 .tRCD = 18,
80 .tRCD = 3,
A Dsdram_elpida.c195 .tRCD = 18,
218 .tRCD = 18,
241 .tRCD = 18,
263 .tRCD = 3,
/u-boot/arch/arm/dts/
A Delpida_ecb240abacn.dtsi13 tRCD-min-tck = <3>;
29 tRCD = <18000>;
51 tRCD = <18000>;
/u-boot/arch/arm/mach-omap2/omap5/
A Demif.c29 .tRCD = 18,
58 .tRCD = 3,
A Dsdram.c617 .tRCD = 18,
639 .tRCD = 3,
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun9i.c128 u32 tRCD; /* in ps */ member
379 const u32 tRCD = PS2CYCLES_ROUNDUP(para->tRCD); in mctl_channel_init() local
550 writel((MCTL_DIV2(tRCD) << 24) | (MCTL_DIV2(tCCD) << 16) | in mctl_channel_init()
644 (tRCD << 12) | (tRP << 8) | (tWTR << 4) | (tRTP << 0), in mctl_channel_init()
890 .tRCD = 13750, in sunxi_dram_init()
/u-boot/board/tbs/tbs2910/
A Dtbs2910.cfg81 /* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
/u-boot/arch/arm/include/asm/
A Demif.h1142 u8 tRCD; member
1171 u32 tRCD; member
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3288-dmc.txt50 rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet
/u-boot/board/buffalo/lsxl/
A Dkwbimage-lschl.cfg56 # bit7-4: 4, 5 cycle tRCD
A Dkwbimage-lsxhl.cfg56 # bit7-4: 4, 5 cycle tRCD
/u-boot/board/d-link/dns325/
A Dkwbimage.cfg53 # bit7-4: 5, 6 cycle tRCD
/u-boot/arch/arm/mach-omap2/
A Demif-common.c723 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; in get_sdram_tim_1_reg()

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