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Searched refs:tWR (Results 1 – 12 of 12) sorted by relevance

/u-boot/arch/arm/mach-omap2/omap4/
A Demif.c28 .tWR = 15,
52 .tWR = 15,
81 .tWR = 3,
A Dsdram_elpida.c196 .tWR = 15,
219 .tWR = 15,
242 .tWR = 15,
264 .tWR = 3,
/u-boot/arch/arm/dts/
A Delpida_ecb240abacn.dtsi14 tWR-min-tck = <3>;
30 tWR = <15000>;
52 tWR = <15000>;
/u-boot/arch/arm/mach-omap2/omap5/
A Demif.c30 .tWR = 15,
59 .tWR = 3,
A Dsdram.c618 .tWR = 15,
640 .tWR = 3,
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun9i.c125 u32 tWR; /* in nCK */ member
388 const u32 tWR = NS2CYCLES_FLOOR(para->tWR); in mctl_channel_init() local
462 mr[0] = DDR3_MR0_PPD_FAST_EXIT | DDR3_MR0_WR(tWR) | in mctl_channel_init()
898 .tWR = 15, in sunxi_dram_init()
/u-boot/board/tbs/tbs2910/
A Dtbs2910.cfg81 /* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
/u-boot/arch/arm/include/asm/
A Demif.h1143 u8 tWR; member
1172 u32 tWR; member
/u-boot/board/buffalo/lsxl/
A Dkwbimage-lschl.cfg58 # bit15-12: 4, 5 cyle tWR
A Dkwbimage-lsxhl.cfg58 # bit15-12: 5, 6 cyle tWR
/u-boot/board/d-link/dns325/
A Dkwbimage.cfg55 # bit15-12: 5, 6 cyle tWR
/u-boot/arch/arm/mach-omap2/
A Demif-common.c720 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; in get_sdram_tim_1_reg()

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