Searched refs:tap_val (Results 1 – 3 of 3) sorted by relevance
| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | ddr.c | 191 mod_val_init, cycle_val, tap_val, ctl_config; in qca956x_ddr_init() local
202 tap_val = CFG_DDR2_TAP_VAL; in qca956x_ddr_init()
301 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); in qca956x_ddr_init()
302 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); in qca956x_ddr_init()
303 writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL2); in qca956x_ddr_init()
304 writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL3); in qca956x_ddr_init()
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| /u-boot/arch/mips/mach-ath79/qca953x/ |
| A D | ddr.c | 414 u32 val, pass, tap, cnt, tap_val, last, first; in ddr_tap_tuning() local
419 tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
465 tap_val = (first + last) / 2; in ddr_tap_tuning()
466 tap_val %= DDR_TAP_MAX_VAL; in ddr_tap_tuning()
469 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
470 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /u-boot/drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_ip_engine.c | 651 int tap_val, max_val = -10000, min_val = 10000; in ddr3_tip_process_result() local
666 tap_val = GET_TAP_RESULT(ar_result[i], e_edge); in ddr3_tip_process_result()
667 if (tap_val > max_val) in ddr3_tip_process_result()
668 max_val = tap_val; in ddr3_tip_process_result()
669 if (tap_val < min_val) in ddr3_tip_process_result()
670 min_val = tap_val; in ddr3_tip_process_result()
678 i, ar_result[i], tap_val, in ddr3_tip_process_result()
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