| /u-boot/arch/arm/mach-sunxi/dram_timings/ |
| A D | h6_ddr3_1333.c | 69 u8 tcke = max(ns_to_t(6), 3); /* JEDEC: max(5.625 ns, 3nCK) */ in mctl_set_timing_params() local
72 u8 tckesr = tcke + 1; /* JEDEC: tCKE(min) + 1nCK */ in mctl_set_timing_params()
107 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, in mctl_set_timing_params()
126 writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]); in mctl_set_timing_params()
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| A D | h616_ddr3_1333.c | 39 u8 tcke = max(ns_to_t(6), 3); /* JEDEC: max(5.625 ns, 3nCK) */ in mctl_set_timing_params() local
42 u8 tckesr = tcke + 1; /* JEDEC: tCKE(min) + 1nCK */ in mctl_set_timing_params()
65 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, in mctl_set_timing_params()
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| A D | h6_lpddr3.c | 54 u8 tcke = 3; in mctl_set_timing_params() local
95 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, in mctl_set_timing_params()
114 writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]); in mctl_set_timing_params()
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| A D | ddr3_1333.c | 27 u8 tcke = 3; in mctl_set_timing_params() local
70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| A D | lpddr3_stock.c | 27 u8 tcke = 3; in mctl_set_timing_params() local
66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| A D | ddr2_v3s.c | 27 u8 tcke = 3; in mctl_set_timing_params() local
67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_rk3288.h | 65 u32 tcke; member
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| A D | sdram_rk3036.h | 66 u32 tcke; member
263 u32 tcke; member
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| A D | sdram_rk322x.h | 99 u32 tcke; member
225 u32 tcke; member
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| A D | ddr_rk3368.h | 76 u32 tcke; member
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| A D | ddr_rk3288.h | 67 u32 tcke; member
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| /u-boot/arch/arm/include/asm/arch-tegra20/ |
| A D | emc.h | 50 u32 tcke; /* 0x94: EMC_TCKE */ member
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| /u-boot/arch/arm/include/asm/arch-vf610/ |
| A D | ddrmc-vf610.h | 34 u8 tcke; member
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| /u-boot/board/phytec/pcm052/ |
| A D | pcm052.c | 114 .tcke = 3, in dram_init()
169 .tcke = 3, in dram_init()
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| /u-boot/arch/arm/include/asm/arch-omap3/ |
| A D | mem.h | 82 #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ argument
84 ACTIM_CTRLB_TCKE(tcke) | \
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| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 1046 u8 tcke, tcksrx, tcksre, trrd; in mx6_lpddr2_cfg() local
1090 tcke = 3; in mx6_lpddr2_cfg()
1128 debug("tcke=%d\n", tcke); in mx6_lpddr2_cfg()
1247 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_lpddr2_cfg()
1278 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; in mx6_ddr3_cfg() local
1352 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1363 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1; in mx6_ddr3_cfg()
1397 debug("tcke=%d\n", tcke); in mx6_ddr3_cfg()
1550 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_ddr3_cfg()
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a33.c | 113 u8 tcke = 3; in auto_set_timing_para() local
150 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
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| A D | dram_sun8i_a83t.c | 113 u8 tcke = 3; in auto_set_timing_para() local
182 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
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| A D | dram_sun6i.c | 232 writel(MCTL_TCKE, &mctl_ctl->tcke); in mctl_channel_init()
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| /u-boot/arch/arm/mach-imx/ |
| A D | ddrmc-vf610.c | 140 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]); in ddrmc_ctrl_init_ddr3()
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| /u-boot/board/freescale/vf610twr/ |
| A D | vf610twr.c | 108 .tcke = 3, in dram_init()
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| /u-boot/board/toradex/colibri_vf/ |
| A D | colibri_vf.c | 109 .tcke = 3, in dram_init()
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sun6i.h | 99 u32 tcke; /* 0x12c */ member
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 81 tcke
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| /u-boot/drivers/ram/rockchip/ |
| A D | dmc-rk3368.c | 518 pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq)); in pctl_calc_timings()
523 pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */ in pctl_calc_timings()
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