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Searched refs:tcksrx (Results 1 – 19 of 19) sorted by relevance

/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dh616_ddr3_1333.c40 u8 tcksrx = max(ns_to_t(10), 4); /* JEDEC: max(10 ns, 5nCK) */ in mctl_set_timing_params() local
65 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, in mctl_set_timing_params()
A Dddr3_1333.c28 u8 tcksrx = 5; in mctl_set_timing_params() local
69 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | in mctl_set_timing_params()
A Dlpddr3_stock.c28 u8 tcksrx = 5; in mctl_set_timing_params() local
65 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | in mctl_set_timing_params()
A Dddr2_v3s.c28 u8 tcksrx = 5; in mctl_set_timing_params() local
66 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | in mctl_set_timing_params()
A Dh6_lpddr3.c55 u8 tcksrx = 5; in mctl_set_timing_params() local
95 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, in mctl_set_timing_params()
A Dh6_ddr3_1333.c70 u8 tcksrx = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */ in mctl_set_timing_params() local
107 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, in mctl_set_timing_params()
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dsdram_rk3288.h64 u32 tcksrx; member
A Dsdram_rk3036.h65 u32 tcksrx; member
262 u32 tcksrx; member
A Dsdram_rk322x.h98 u32 tcksrx; member
224 u32 tcksrx; member
A Dddr_rk3368.h75 u32 tcksrx; member
A Dddr_rk3288.h66 u32 tcksrx; member
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun8i_a33.c114 u8 tcksrx = 5; in auto_set_timing_para() local
150 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
A Ddram_sun8i_a83t.c114 u8 tcksrx = 5; in auto_set_timing_para() local
182 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
A Ddram_sun6i.c231 writel(MCTL_TCKSRX, &mctl_ctl->tcksrx); in mctl_channel_init()
/u-boot/arch/arm/mach-imx/mx6/
A Dddr.c1046 u8 tcke, tcksrx, tcksre, trrd; in mx6_lpddr2_cfg() local
1099 tcksrx = tcksre; in mx6_lpddr2_cfg()
1129 debug("tcksrx=%d\n", tcksrx); in mx6_lpddr2_cfg()
1251 (tcksrx & 0x7) << 3 | in mx6_lpddr2_cfg()
1278 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; in mx6_ddr3_cfg() local
1380 tcksrx = tcksre; in mx6_ddr3_cfg()
1398 debug("tcksrx=%d\n", tcksrx); in mx6_ddr3_cfg()
1554 (tcksrx & 0x7) << 3 | in mx6_ddr3_cfg()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sun6i.h98 u32 tcksrx; /* 0x128 */ member
/u-boot/drivers/ddr/fsl/
A Dctrl_regs.c2002 unsigned int txpr, tcksre, tcksrx; in set_timing_cfg_7() local
2008 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); in set_timing_cfg_7()
2033 if (tcksrx <= 19) in set_timing_cfg_7()
2034 cksrx = tcksrx - 5; in set_timing_cfg_7()
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3288-dmc.txt80 tcksrx
/u-boot/drivers/ram/rockchip/
A Ddmc-rk3368.c517 pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq)); in pctl_calc_timings()

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