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Searched refs:tdinit0 (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dddr3_1333.c38 u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ in mctl_set_timing_params() local
82 writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); in mctl_set_timing_params()
A Dlpddr3_stock.c38 u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ in mctl_set_timing_params() local
78 writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); in mctl_set_timing_params()
A Dddr2_v3s.c38 u32 tdinit0 = (400 * CONFIG_DRAM_CLK) + 1; /* 400us */ in mctl_set_timing_params() local
79 writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); in mctl_set_timing_params()
A Dh6_lpddr3.c68 u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ in mctl_set_timing_params() local
127 writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]); in mctl_set_timing_params()
A Dh6_ddr3_1333.c82 u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ in mctl_set_timing_params() local
139 writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]); in mctl_set_timing_params()
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun8i_a83t.c123 u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ in auto_set_timing_para() local
163 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ in auto_set_timing_para()
197 writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); in auto_set_timing_para()
A Ddram_sun9i.c666 const unsigned int tdinit0 = 500 * CONFIG_DRAM_CLK; /* 500us */ in mctl_channel_init() local
672 writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]); in mctl_channel_init()
676 const unsigned int tdinit0 = (100 * CONFIG_DRAM_CLK + 999) / in mctl_channel_init() local
682 writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]); in mctl_channel_init()
A Ddram_sun8i_a33.c123 u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ in auto_set_timing_para() local
165 writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); in auto_set_timing_para()

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