| /u-boot/board/freescale/corenet_ds/ |
| A D | p4080ds_ddr.c | 90 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
122 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
154 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
186 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
218 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
250 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
282 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
314 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
|
| /u-boot/drivers/ddr/fsl/ |
| A D | mpc85xx_ddr_gen1.c | 48 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
|
| A D | mpc86xx_ddr.c | 56 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
|
| A D | mpc85xx_ddr_gen3.c | 128 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
214 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); in fsl_ddr_set_memctl_regs()
339 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
513 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); in fsl_ddr_set_memctl_regs()
515 in_be32(&ddr->timing_cfg_2)); in fsl_ddr_set_memctl_regs()
|
| A D | mpc85xx_ddr_gen2.c | 70 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
|
| A D | arm_ddr_gen3.c | 96 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
|
| /u-boot/board/sbc8641d/ |
| A D | sbc8641d.c | 116 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
147 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; in fixed_sdram()
|
| /u-boot/board/socrates/ |
| A D | sdram.c | 41 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
|
| /u-boot/board/kontron/sl28/ |
| A D | ddr.c | 30 .timing_cfg_2 = 0x0fc0d118,
|
| /u-boot/board/freescale/p1010rdb/ |
| A D | ddr.c | 29 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
56 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
|
| /u-boot/board/freescale/ls1043ardb/ |
| A D | ddr.h | 62 .timing_cfg_2 = 0x0048C111,
|
| /u-boot/board/freescale/mpc8349emds/ |
| A D | mpc8349emds.c | 110 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
135 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
|
| /u-boot/board/freescale/mpc8349itx/ |
| A D | mpc8349itx.c | 69 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ in fixed_sdram()
83 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); in fixed_sdram()
|
| /u-boot/board/sbc8548/ |
| A D | ddr.c | 108 out_be32(&ddr->timing_cfg_2, 0x0fa044C7); in fixed_sdram()
|
| /u-boot/board/mpc8308_p1m/ |
| A D | sdram.c | 47 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
|
| /u-boot/board/freescale/mpc8308rdb/ |
| A D | sdram.c | 51 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
|
| /u-boot/board/gdsys/mpc8308/ |
| A D | sdram.c | 54 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
|
| /u-boot/board/freescale/mpc8315erdb/ |
| A D | sdram.c | 69 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
|
| /u-boot/board/freescale/mpc8313erdb/ |
| A D | sdram.c | 78 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
|
| /u-boot/board/freescale/mpc832xemds/ |
| A D | mpc832xemds.c | 142 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
|
| /u-boot/board/Arcturus/ucp1020/ |
| A D | ddr.c | 94 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, in fixed_sdram()
|
| /u-boot/board/sbc8349/ |
| A D | sbc8349.c | 109 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
|
| /u-boot/board/freescale/ls1021aiot/ |
| A D | ls1021aiot.c | 63 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
|
| /u-boot/board/freescale/ls1021atsn/ |
| A D | ls1021atsn.c | 41 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
|
| /u-boot/board/freescale/mpc8323erdb/ |
| A D | mpc8323erdb.c | 123 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
|