Searched refs:timing_cfg_5 (Results 1 – 16 of 16) sorted by relevance
| /u-boot/board/freescale/corenet_ds/ |
| A D | p4080ds_ddr.c | 102 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
134 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
166 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
198 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
230 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
262 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
294 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
326 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /u-boot/board/kontron/sl28/ |
| A D | ddr.c | 48 .timing_cfg_5 = 0x04401400,
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| /u-boot/board/freescale/p1010rdb/ |
| A D | ddr.c | 41 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
68 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /u-boot/board/freescale/ls1043ardb/ |
| A D | ddr.h | 88 .timing_cfg_5 = 0x03401400,
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| /u-boot/drivers/ddr/fsl/ |
| A D | arm_ddr_gen3.c | 110 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen3.c | 142 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
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| A D | fsl_ddr_gen4.c | 172 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
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| A D | ctrl_regs.c | 1969 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1975 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); in set_timing_cfg_5()
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| A D | interactive.c | 663 CFG_REGS(timing_cfg_5), in print_fsl_memctl_config_regs()
754 CFG_REGS(timing_cfg_5), in fsl_ddr_regs_edit()
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| /u-boot/board/Arcturus/ucp1020/ |
| A D | ddr.c | 106 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /u-boot/board/freescale/ls1021aiot/ |
| A D | ls1021aiot.c | 66 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
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| /u-boot/board/freescale/ls1021atsn/ |
| A D | ls1021atsn.c | 44 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | ddr.c | 235 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /u-boot/include/ |
| A D | fsl_immap.h | 51 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ member
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| A D | fsl_ddr_sdram.h | 278 unsigned int timing_cfg_5; member
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| /u-boot/board/freescale/ls1021atwr/ |
| A D | ls1021atwr.c | 160 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
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