Searched refs:timing_cfg_7 (Results 1 – 6 of 6) sorted by relevance

/u-boot/board/freescale/ls1043ardb/
A D	ddr.h	90 .timing_cfg_7 = 0x13300000,
/u-boot/include/
A D	fsl_immap.h	53 u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ member
A D	fsl_ddr_sdram.h	280 unsigned int timing_cfg_7; member
/u-boot/drivers/ddr/fsl/
A D	fsl_ddr_gen4.c	174 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); in fsl_ddr_set_memctl_regs()
A D	ctrl_regs.c	2038 ddr->timing_cfg_7 = (0 in set_timing_cfg_7() 2045 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); in set_timing_cfg_7()
A D	interactive.c	666 CFG_REGS(timing_cfg_7), in print_fsl_memctl_config_regs() 757 CFG_REGS(timing_cfg_7), in fsl_ddr_regs_edit()

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