Searched refs:timing_cfg_8 (Results 1 – 6 of 6) sorted by relevance

/u-boot/board/freescale/ls1043ardb/
A D	ddr.h	91 .timing_cfg_8 = 0x02115600,
/u-boot/include/
A D	fsl_immap.h	85 u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ member
A D	fsl_ddr_sdram.h	281 unsigned int timing_cfg_8; member
/u-boot/drivers/ddr/fsl/
A D	fsl_ddr_gen4.c	175 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); in fsl_ddr_set_memctl_regs()
A D	ctrl_regs.c	2087 ddr->timing_cfg_8 = (0 in set_timing_cfg_8() 2097 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); in set_timing_cfg_8()
A D	interactive.c	667 CFG_REGS(timing_cfg_8), in print_fsl_memctl_config_regs() 758 CFG_REGS(timing_cfg_8), in fsl_ddr_regs_edit()

Completed in 15 milliseconds

Last Index update Sat Jun 03 09:59:21 CST 2023