Searched refs:timing_cfg_9 (Results 1 – 6 of 6) sorted by relevance

/u-boot/board/freescale/ls1043ardb/
A D	ddr.h	92 .timing_cfg_9 = 0,
/u-boot/include/
A D	fsl_immap.h	86 u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ member
A D	fsl_ddr_sdram.h	282 unsigned int timing_cfg_9; member
/u-boot/drivers/ddr/fsl/
A D	fsl_ddr_gen4.c	176 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); in fsl_ddr_set_memctl_regs()
A D	ctrl_regs.c	2114 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 | in set_timing_cfg_9() 2117 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); in set_timing_cfg_9()
A D	interactive.c	668 CFG_REGS(timing_cfg_9), in print_fsl_memctl_config_regs() 759 CFG_REGS(timing_cfg_9), in fsl_ddr_regs_edit()

Completed in 15 milliseconds

Last Index update Sat Jun 03 09:59:21 CST 2023