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Searched refs:tlb_addr (Results 1 – 14 of 14) sorted by relevance

/u-boot/arch/arm/lib/
A Dcache-cp15.c33 u64 *page_table = (u64 *)gd->arch.tlb_addr; in set_section_phys()
37 u32 *page_table = (u32 *)gd->arch.tlb_addr; in set_section_phys()
65 u64 *page_table = (u64 *)gd->arch.tlb_addr; in mmu_set_region_dcache_behaviour_phys()
67 u32 *page_table = (u32 *)gd->arch.tlb_addr; in mmu_set_region_dcache_behaviour_phys()
141 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4)); in mmu_setup()
142 u64 tpt = gd->arch.tlb_addr + (4096 * i); in mmu_setup()
162 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0) in mmu_setup()
174 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0) in mmu_setup()
191 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; in mmu_setup()
204 : : "r" (gd->arch.tlb_addr) : "memory"); in mmu_setup()
A Dcache.c151 gd->arch.tlb_addr = gd->relocaddr; in arm_reserve_mmu()
152 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, in arm_reserve_mmu()
153 gd->arch.tlb_addr + gd->arch.tlb_size); in arm_reserve_mmu()
160 gd->arch.tlb_allocated = gd->arch.tlb_addr; in arm_reserve_mmu()
A Dbdinfo.c32 bdinfo_print_num_l("TLB addr", gd->arch.tlb_addr); in arch_print_bdinfo()
/u-boot/arch/arm/cpu/armv8/
A Dcache_v8.c126 pte = (u64*)gd->arch.tlb_addr; in find_pte()
158 gd->arch.tlb_fillptr - gd->arch.tlb_addr, in create_table()
389 u64 tlb_addr = gd->arch.tlb_addr; in setup_all_pgtables() local
393 gd->arch.tlb_fillptr = tlb_addr; in setup_all_pgtables()
400 (uintptr_t)gd->arch.tlb_addr; in setup_all_pgtables()
401 gd->arch.tlb_addr = gd->arch.tlb_fillptr; in setup_all_pgtables()
403 gd->arch.tlb_emerg = gd->arch.tlb_addr; in setup_all_pgtables()
404 gd->arch.tlb_addr = tlb_addr; in setup_all_pgtables()
599 __asm_switch_ttbr(gd->arch.tlb_addr); in mmu_set_region_dcache_behaviour()
638 flush_dcache_range(gd->arch.tlb_addr, in mmu_change_region_attr()
[all …]
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dspl.c119 gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1); in board_init_f()
120 gd->arch.tlb_allocated = gd->arch.tlb_addr; in board_init_f()
A Dcpu.c443 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; in early_mmu_setup()
445 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; in early_mmu_setup()
446 gd->arch.tlb_fillptr = gd->arch.tlb_addr; in early_mmu_setup()
453 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, in early_mmu_setup()
519 u64 tlb_addr_save = gd->arch.tlb_addr; in final_mmu_setup()
583 tlb_addr_save = gd->arch.tlb_addr; in final_mmu_setup()
587 gd->arch.tlb_addr = tlb_addr_save; in final_mmu_setup()
599 gd->arch.tlb_addr = gd->arch.tlb_fillptr; in final_mmu_setup()
600 gd->arch.tlb_emerg = gd->arch.tlb_addr; in final_mmu_setup()
602 gd->arch.tlb_addr = tlb_addr_save; in final_mmu_setup()
[all …]
/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dcpu.c152 u32 *level0_table = (u32 *)gd->arch.tlb_addr; in mmu_setup()
153 u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000); in mmu_setup()
215 mmu_page_table_flush(gd->arch.tlb_addr, in enable_caches()
216 gd->arch.tlb_addr + gd->arch.tlb_size); in enable_caches()
/u-boot/arch/arm/include/asm/
A Dglobal_data.h48 unsigned long tlb_addr; member
/u-boot/arch/arm/mach-k3/
A Dcommon.c458 gd->arch.tlb_addr = ram_top - gd->arch.tlb_size; in spl_enable_dcache()
459 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, in spl_enable_dcache()
460 gd->arch.tlb_addr + gd->arch.tlb_size); in spl_enable_dcache()
/u-boot/arch/arm/mach-versal/
A Dcpu.c118 gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR; in arm_reserve_mmu()
/u-boot/arch/arm/mach-zynqmp/
A Dcpu.c127 gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; in arm_reserve_mmu()
/u-boot/drivers/ddr/altera/
A Dsdram_soc64.c150 gd->arch.tlb_addr = start_addr + PGTABLE_OFF; in sdram_init_ecc_bits()
A Dsdram_arria10.c202 gd->arch.tlb_addr = 0x4000; in sdram_init_ecc_bits()
/u-boot/arch/arm/mach-stm32mp/
A Dcpu.c228 gd->arch.tlb_addr = (unsigned long)&early_tlb; in early_enable_caches()

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