tmrw (reference) in projects: u-boot - OpenGrok search results

Searched refs:tmrw (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/arm/mach-sunxi/dram_timings/
A D	h616_ddr3_1333.c	`36 u8 tmrw = 0; /* ? */ in mctl_set_timing_params() local 62 writel((tmrw << 20) \| (tmrd << 12) \| tmod, &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()`
A D	ddr3_1333.c	`24 u8 tmrw = 0; in mctl_set_timing_params() local 65 writel(DRAMTMG3_TMRW(tmrw) \| DRAMTMG3_TMRD(tmrd) \| DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()`
A D	lpddr3_stock.c	`24 u8 tmrw = 5; in mctl_set_timing_params() local 61 writel(DRAMTMG3_TMRW(tmrw) \| DRAMTMG3_TMRD(tmrd) \| DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()`
A D	ddr2_v3s.c	`24 u8 tmrw = 0; in mctl_set_timing_params() local 62 writel(DRAMTMG3_TMRW(tmrw) \| DRAMTMG3_TMRD(tmrd) \| DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()`
A D	h6_lpddr3.c	`51 u8 tmrw = 5; in mctl_set_timing_params() local 92 writel((tmrw << 20) \| (tmrd << 12) \| tmod, &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()`
A D	h6_ddr3_1333.c	`66 u8 tmrw = 0; /* ? */ in mctl_set_timing_params() local 104 writel((tmrw << 20) \| (tmrd << 12) \| tmod, &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()`
/u-boot/arch/arm/mach-sunxi/
A D	dram_sun8i_a83t.c	`110 u8 tmrw = 0; in auto_set_timing_para() local 158 tmrw = 5; in auto_set_timing_para() 178 reg_val = (tmrw << 16) \| (tmrd << 12) \| (tmod << 0); in auto_set_timing_para()`
A D	dram_sun8i_a33.c	`110 u8 tmrw = 0; in auto_set_timing_para() local 146 reg_val = (tmrw << 16) \| (tmrd << 12) \| (tmod << 0); in auto_set_timing_para()`

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