| /u-boot/board/work-microwave/work_92105/ |
| A D | work_92105_spl.c | 24 .tras = 20833333,
44 .tras = 22222222,
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| /u-boot/arch/arm/mach-sunxi/dram_timings/ |
| A D | h6_lpddr3.c | 38 u8 tras = ns_to_t(42); in mctl_set_timing_params() local
87 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, in mctl_set_timing_params()
111 writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), in mctl_set_timing_params()
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| A D | h6_ddr3_1333.c | 59 u8 tras = ns_to_t(38); /* JEDEC >= 36 ns, <= 9*trefi */ in mctl_set_timing_params() local
99 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, in mctl_set_timing_params()
123 writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), in mctl_set_timing_params()
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| A D | h616_ddr3_1333.c | 31 u8 tras = ns_to_t(38); /* JEDEC >= 36 ns, <= 9*trefi */ in mctl_set_timing_params() local
57 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, in mctl_set_timing_params()
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| A D | ddr3_1333.c | 20 u8 tras = ns_to_t(38); in mctl_set_timing_params() local
58 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), in mctl_set_timing_params()
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| A D | lpddr3_stock.c | 20 u8 tras = ns_to_t(42); in mctl_set_timing_params() local
54 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), in mctl_set_timing_params()
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| A D | ddr2_v3s.c | 20 u8 tras = ns_to_t(45); in mctl_set_timing_params() local
55 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), in mctl_set_timing_params()
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| /u-boot/board/timll/devkit3250/ |
| A D | devkit3250_spl.c | 31 .tras = 23809524,
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| /u-boot/include/ |
| A D | spd.h | 45 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
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| A D | ddr_spd.h | 45 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
107 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_rk3288.h | 50 u32 tras; member
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| A D | sdram_rk3036.h | 51 u32 tras; member
248 u32 tras; member
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| A D | sdram_rk322x.h | 84 u32 tras; member
210 u32 tras; member
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| A D | ddr_rk3368.h | 61 u32 tras; member
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| A D | ddr_rk3288.h | 52 u32 tras; member
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| /u-boot/drivers/ram/ |
| A D | stm32_sdram.c | 129 u8 tras; member
207 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
217 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
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| /u-boot/arch/arm/mach-lpc32xx/ |
| A D | dram.c | 43 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
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| /u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| A D | emc.h | 85 u32 tras; member
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a83t.c | 104 u8 tras = ns_to_t(38); in auto_set_timing_para() local
155 tras = ns_to_t(42); in auto_set_timing_para()
172 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
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| A D | dram_sun8i_a33.c | 104 u8 tras = ns_to_t(38); in auto_set_timing_para() local
140 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
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| /u-boot/doc/device-tree-bindings/memory-controllers/ |
| A D | st,stm32-fmc.txt | 21 tras
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| /u-boot/arch/arm/include/asm/arch-omap3/ |
| A D | mem.h | 66 #define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ argument
69 ACTIM_CTRLA_TRAS(tras) | \
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| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 1048 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1106 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1; in mx6_lpddr2_cfg()
1136 debug("tras=%d\n", tras); in mx6_lpddr2_cfg()
1190 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl; in mx6_lpddr2_cfg()
1281 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; in mx6_ddr3_cfg() local
1385 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1; in mx6_ddr3_cfg()
1414 debug("tras=%d\n", tras); in mx6_ddr3_cfg()
1485 (tras << 16) | (1 << 15) /* trpa */ | in mx6_ddr3_cfg()
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| /u-boot/drivers/ddr/fsl/ |
| A D | ddr1_dimm_params.c | 310 pdimm->tras_ps = spd->tras * 1000; in ddr_compute_dimm_parameters()
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| A D | ddr2_dimm_params.c | 309 pdimm->tras_ps = spd->tras * 1000; in ddr_compute_dimm_parameters()
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