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Searched refs:trcd (Results 1 – 25 of 65) sorted by relevance

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/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dh6_lpddr3.c31 u8 trcd = max(ns_to_t(24), 2); in mctl_set_timing_params() local
93 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, in mctl_set_timing_params()
118 writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); in mctl_set_timing_params()
A Dh6_ddr3_1333.c52 u8 trcd = ns_to_t(15); /* JEDEC: 13.5 ns */ in mctl_set_timing_params() local
105 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, in mctl_set_timing_params()
130 writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); in mctl_set_timing_params()
A Dh616_ddr3_1333.c26 u8 trcd = ns_to_t(15); /* JEDEC: 13.5 ns */ in mctl_set_timing_params() local
63 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, in mctl_set_timing_params()
A Dddr3_1333.c13 u8 trcd = ns_to_t(15); in mctl_set_timing_params() local
67 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
A Dlpddr3_stock.c13 u8 trcd = max(ns_to_t(24), 2); in mctl_set_timing_params() local
63 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
A Dddr2_v3s.c13 u8 trcd = ns_to_t(20); in mctl_set_timing_params() local
64 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
/u-boot/arch/arm/mach-imx/mx6/
A Dopos6ul.c145 .trcd = 1500,
186 mem_ddr.trcd = 1375; in spl_dram_init()
A Dlitesom.c145 .trcd = 1375,
/u-boot/include/
A Dspd.h44 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ member
/u-boot/board/gateworks/gw_ventana/
A Dgw_ventana_spl.c161 .trcd = 1375,
175 .trcd = 1375,
189 .trcd = 1375,
203 .trcd = 1375,
/u-boot/board/freescale/mx6memcal/
A Dspl.c256 .trcd = 1375,
270 .trcd = 1375,
284 .trcd = 1375,
298 .trcd = 1350,
/u-boot/board/bachmann/ot1200/
A Dot1200_spl.c99 .trcd = 1375,
/u-boot/board/ccv/xpress/
A Dspl.c75 .trcd = 1375,
/u-boot/board/compulab/cm_fx6/
A Dspl.c119 .trcd = 1800,
188 .trcd = 1324,
/u-boot/board/barco/platinum/
A Dspl_picon.c94 .trcd = 1375,
A Dspl_titanium.c94 .trcd = 1375,
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dsdram_rk3288.h52 u32 trcd; member
/u-boot/board/technexion/pico-imx6/
A Dspl.c150 .trcd = 1500,
164 .trcd = 1500,
/u-boot/drivers/ram/
A Dstm32_sdram.c133 u8 trcd; member
203 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
213 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
/u-boot/board/ge/b1x5v2/
A Dspl.c263 .trcd = 1310,
276 .trcd = 1310,
289 .trcd = 1310,
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3288-dmc.txt50 rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet
68 trcd
142 rockchip,trcd = <10>;
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun8i_a83t.c97 u8 trcd = ns_to_t(15); in auto_set_timing_para() local
149 trcd = max(ns_to_t(24), 2); in auto_set_timing_para()
180 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
/u-boot/board/bticino/mamoj/
A Dspl.c101 .trcd = 1375,
/u-boot/doc/device-tree-bindings/memory-controllers/
A Dst,stm32-fmc.txt24 trcd
/u-boot/board/engicam/common/
A Dspl.c214 .trcd = 1375,
364 .trcd = 1375,

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