| /u-boot/board/work-microwave/work_92105/ |
| A D | work_92105_spl.c | 30 .trrd = 1,
50 .trrd = 1,
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| /u-boot/arch/arm/mach-sunxi/dram_timings/ |
| A D | h6_lpddr3.c | 30 u8 trrd = max(ns_to_t(10), 2); in mctl_set_timing_params() local
93 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, in mctl_set_timing_params()
111 writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), in mctl_set_timing_params()
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| A D | h6_ddr3_1333.c | 51 u8 trrd = max(ns_to_t(6), 4); /* JEDEC: max(6 ns, 4nCK) */ in mctl_set_timing_params() local
105 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, in mctl_set_timing_params()
123 writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), in mctl_set_timing_params()
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| A D | h616_ddr3_1333.c | 25 u8 trrd = max(ns_to_t(6), 4); /* JEDEC: max(6 ns, 4nCK) */ in mctl_set_timing_params() local
63 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, in mctl_set_timing_params()
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| A D | ddr3_1333.c | 12 u8 trrd = max(ns_to_t(10), 4); in mctl_set_timing_params() local
67 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
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| A D | lpddr3_stock.c | 12 u8 trrd = max(ns_to_t(10), 2); in mctl_set_timing_params() local
63 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
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| A D | ddr2_v3s.c | 12 u8 trrd = max(ns_to_t(10), 2); in mctl_set_timing_params() local
64 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
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| /u-boot/board/timll/devkit3250/ |
| A D | devkit3250_spl.c | 37 .trrd = 1,
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| /u-boot/include/ |
| A D | spd.h | 43 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ member
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| A D | ddr_spd.h | 43 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ member
105 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ member
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_rk3288.h | 53 u32 trrd; member
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| A D | sdram_rk3036.h | 54 u32 trrd; member
251 u32 trrd; member
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| A D | sdram_rk322x.h | 87 u32 trrd; member
213 u32 trrd; member
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| /u-boot/arch/arm/include/asm/arch-vf610/ |
| A D | ddrmc-vf610.h | 22 u8 trrd; member
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| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 1046 u8 tcke, tcksrx, tcksre, trrd; in mx6_lpddr2_cfg() local
1095 trrd = DIV_ROUND_UP(10000, clkper) - 1; in mx6_lpddr2_cfg()
1142 debug("trrd=%d\n", trrd); in mx6_lpddr2_cfg()
1191 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd; in mx6_lpddr2_cfg()
1278 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; in mx6_ddr3_cfg() local
1355 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1358 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1366 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1369 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1421 debug("trrd=%d\n", trrd); in mx6_ddr3_cfg()
[all …]
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| /u-boot/arch/arm/mach-lpc32xx/ |
| A D | dram.c | 49 writel(dram->trrd, &emc->t_rrd); in ddr_init()
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| /u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| A D | emc.h | 91 u32 trrd; member
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| /u-boot/board/phytec/pcm052/ |
| A D | pcm052.c | 102 .trrd = 4, in dram_init()
157 .trrd = 4, in dram_init()
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a83t.c | 96 u8 trrd = max(ns_to_t(10), 4); in auto_set_timing_para() local
148 trrd = max(ns_to_t(10), 2); in auto_set_timing_para()
180 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
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| A D | dram_sun8i_a33.c | 96 u8 trrd = max(ns_to_t(10), 4); in auto_set_timing_para() local
148 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
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| /u-boot/arch/arm/include/asm/arch-omap3/ |
| A D | mem.h | 66 #define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ argument
72 ACTIM_CTRLA_TRRD(trrd) | \
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| /u-boot/doc/device-tree-bindings/misc/ |
| A D | intel,baytrail-fsp.txt | 85 - fsp,dimm-trrd
148 fsp,dimm-trrd = <6>;
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| /u-boot/drivers/ram/rockchip/ |
| A D | dmc-rk3368.c | 503 pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq)); in pctl_calc_timings()
534 if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) { in pctl_calc_timings()
536 pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq); in pctl_calc_timings()
538 } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) { in pctl_calc_timings()
540 } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) { in pctl_calc_timings()
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| /u-boot/drivers/ddr/fsl/ |
| A D | ddr1_dimm_params.c | 316 pdimm->trrd_ps = spd->trrd * 250; in ddr_compute_dimm_parameters()
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| A D | ddr2_dimm_params.c | 315 pdimm->trrd_ps = spd->trrd * 250; in ddr_compute_dimm_parameters()
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