Searched refs:tx_channel (Results 1 – 5 of 5) sorted by relevance
173 WRITE_ONCE(ivc->tx_channel->w_count, in tegra_ivc_advance_tx()174 READ_ONCE(ivc->tx_channel->w_count) + 1); in tegra_ivc_advance_tx()194 if (ivc->tx_channel->state != ivc_state_established) in tegra_ivc_check_read()215 if (ivc->tx_channel->state != ivc_state_established) in tegra_ivc_check_write()218 if (!tegra_ivc_channel_full(ivc, ivc->tx_channel)) in tegra_ivc_check_write()375 ivc->tx_channel->w_count = 0; in tegra_ivc_channel_notified()391 ivc->tx_channel->state = ivc_state_ack; in tegra_ivc_channel_notified()412 ivc->tx_channel->w_count = 0; in tegra_ivc_channel_notified()429 ivc->tx_channel->state = ivc_state_established; in tegra_ivc_channel_notified()451 ivc->tx_channel->state = ivc_state_established; in tegra_ivc_channel_notified()[all …]
54 struct tegra_ivc_channel_header *tx_channel; member
288 hw_ep->tx_channel ? "dma" : "pio"); in musb_start_urb()290 if (!hw_ep->tx_channel) in musb_start_urb()387 if (ep->tx_channel) { in musb_advance_schedule()388 dma->channel_release(ep->tx_channel); in musb_advance_schedule()389 ep->tx_channel = NULL; in musb_advance_schedule()625 struct dma_channel *channel = hw_ep->tx_channel; in musb_tx_dma_program()673 hw_ep->tx_channel = NULL; in musb_tx_dma_program()713 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; in musb_ep_program()718 hw_ep->tx_channel = dma_channel; in musb_ep_program()1133 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; in musb_host_tx()[all …]
255 struct dma_channel *tx_channel; member
883 ep->tx_channel ? " DMA" : "", in musb_stage0_irq()885 if (!ep->tx_channel) in musb_stage0_irq()
Completed in 12 milliseconds