Home
last modified time | relevance | path

Searched refs:typ (Results 1 – 25 of 41) sorted by relevance

12

/u-boot/drivers/video/tegra124/
A Ddisplay.c34 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
35 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
36 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
37 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
52 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
67 writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, in update_display_mode()
76 writel(timing->hactive.typ | (timing->vactive.typ << 16), in update_display_mode()
171 writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16), in tegra_dc_sor_disable_win_short_raster()
175 writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16), in tegra_dc_sor_disable_win_short_raster()
183 writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16), in tegra_dc_sor_disable_win_short_raster()
[all …]
/u-boot/drivers/video/sunxi/
A Dlcdc.c22 delay = mode->vfront_porch.typ + mode->vsync_len.typ + in lcdc_get_clk_delay()
23 mode->vback_porch.typ; in lcdc_get_clk_delay()
95 bp = mode->hsync_len.typ + mode->hback_porch.typ; in lcdc_tcon0_mode_set()
96 total = mode->hactive.typ + mode->hfront_porch.typ + bp; in lcdc_tcon0_mode_set()
100 bp = mode->vsync_len.typ + mode->vback_porch.typ; in lcdc_tcon0_mode_set()
101 total = mode->vactive.typ + mode->vfront_porch.typ + bp; in lcdc_tcon0_mode_set()
168 yres = mode->vactive.typ; in lcdc_tcon1_mode_set()
178 bp = mode->hsync_len.typ + mode->hback_porch.typ; in lcdc_tcon1_mode_set()
179 total = mode->hactive.typ + mode->hfront_porch.typ + bp; in lcdc_tcon1_mode_set()
183 bp = mode->vsync_len.typ + mode->vback_porch.typ; in lcdc_tcon1_mode_set()
[all …]
A Dsunxi_de2.c84 u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ); in sunxi_de2_mode_set()
175 writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch); in sunxi_de2_mode_set()
223 uc_priv->xsize = timing.hactive.typ; in sunxi_de2_init()
224 uc_priv->ysize = timing.vactive.typ; in sunxi_de2_init()
230 timing.hactive.typ * timing.vactive.typ * in sunxi_de2_init()
/u-boot/drivers/video/
A Datmel_lcdfb.c138 value = (timing->hactive.typ * timing->vactive.typ * in atmel_fb_init()
170 value |= timing->vfront_porch.typ; in atmel_fb_init()
178 value |= (timing->hback_porch.typ - 1); in atmel_fb_init()
183 value |= timing->vactive.typ - 1; in atmel_fb_init()
222 timing.pixelclock.typ = panel_info.vl_clk; in lcd_ctrl_init()
224 timing.hactive.typ = panel_info.vl_col; in lcd_ctrl_init()
229 timing.vactive.typ = panel_info.vl_row; in lcd_ctrl_init()
231 timing.vback_porch.typ = panel_info.vl_clk; in lcd_ctrl_init()
232 timing.vsync_len.typ = panel_info.vl_clk; in lcd_ctrl_init()
261 uc_priv->xsize = timing->hactive.typ; in atmel_fb_lcd_probe()
[all …]
A Dmxsfb.c79 ret = clk_set_rate(&per_clk, timings->pixelclock.typ); in mxs_lcd_init()
136 timings->vsync_len.typ; in mxs_lcd_init()
148 writel(timings->vback_porch.typ + timings->vfront_porch.typ + in mxs_lcd_init()
149 timings->vsync_len.typ + timings->vactive.typ, in mxs_lcd_init()
152 (timings->hback_porch.typ + timings->hfront_porch.typ + in mxs_lcd_init()
153 timings->hsync_len.typ + timings->hactive.typ), in mxs_lcd_init()
155 writel(((timings->hback_porch.typ + timings->hsync_len.typ) << in mxs_lcd_init()
157 (timings->vback_porch.typ + timings->vsync_len.typ), in mxs_lcd_init()
396 uc_priv->xsize = timings.hactive.typ; in mxs_video_probe()
397 uc_priv->ysize = timings.vactive.typ; in mxs_video_probe()
[all …]
A Dtdo-tl070wsh30.c23 .pixelclock.typ = 47250000,
24 .hactive.typ = 1024,
25 .hfront_porch.typ = 46,
26 .hback_porch.typ = 100,
27 .hsync_len.typ = 80,
28 .vactive.typ = 600,
29 .vfront_porch.typ = 5,
30 .vback_porch.typ = 20,
31 .vsync_len.typ = 5,
A Dmali_dp.c166 MALIDP_V_SYNCWIDTH(timings->vsync_len.typ); in malidp_setup_timings()
169 val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) | in malidp_setup_timings()
170 MALIDP_H_FRONTPORCH(timings->hfront_porch.typ); in malidp_setup_timings()
173 val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) | in malidp_setup_timings()
174 MALIDP_V_FRONTPORCH(timings->vfront_porch.typ); in malidp_setup_timings()
177 val = MALIDP_H_ACTIVE(timings->hactive.typ) | in malidp_setup_timings()
178 MALIDP_V_ACTIVE(timings->vactive.typ); in malidp_setup_timings()
213 val = MALIDP_CMP_V_SIZE(timings->vactive.typ) | in malidp_setup_layer()
214 MALIDP_CMP_H_SIZE(timings->hactive.typ); in malidp_setup_layer()
218 val = MALIDP_IN_V_SIZE(timings->vactive.typ) | in malidp_setup_layer()
[all …]
A Dorisetech_otm8009a.c68 .pixelclock.typ = 29700000,
69 .hactive.typ = 480,
70 .hfront_porch.typ = 98,
71 .hback_porch.typ = 98,
72 .hsync_len.typ = 32,
73 .vactive.typ = 800,
74 .vfront_porch.typ = 15,
75 .vback_porch.typ = 14,
76 .vsync_len.typ = 10,
224 default_timing.hactive.typ - 1); in otm8009a_init_sequence()
[all …]
A Datmel_hlcdfb.c331 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
332 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
395 value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ); in atmel_hlcdc_init()
404 value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1); in atmel_hlcdc_init()
405 value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1); in atmel_hlcdc_init()
495 uc_priv->xsize = priv->timing.hactive.typ; in atmel_hlcdc_probe()
496 uc_priv->ysize = priv->timing.vactive.typ; in atmel_hlcdc_probe()
523 if (priv->timing.hactive.typ > LCD_MAX_WIDTH) in atmel_hlcdc_of_to_plat()
524 priv->timing.hactive.typ = LCD_MAX_WIDTH; in atmel_hlcdc_of_to_plat()
526 if (priv->timing.vactive.typ > LCD_MAX_HEIGHT) in atmel_hlcdc_of_to_plat()
[all …]
A Dtda19988.c390 line_clocks = timing->hsync_len.typ + timing->hback_porch.typ + in tda19988_enable()
391 timing->hactive.typ + timing->hfront_porch.typ; in tda19988_enable()
392 lines = timing->vsync_len.typ + timing->vback_porch.typ + in tda19988_enable()
393 timing->vactive.typ + timing->vfront_porch.typ; in tda19988_enable()
458 timing->vfront_porch.typ); in tda19988_enable()
460 timing->hfront_porch.typ); in tda19988_enable()
462 timing->vfront_porch.typ + in tda19988_enable()
463 timing->vsync_len.typ); in tda19988_enable()
465 timing->hfront_porch.typ); in tda19988_enable()
471 timing->hfront_porch.typ); in tda19988_enable()
[all …]
A Ddw_mipi_dsi.c234 u32 htotal = timings->hactive.typ + timings->hfront_porch.typ + in dsi_mode_vrefresh()
235 timings->hback_porch.typ + timings->hsync_len.typ; in dsi_mode_vrefresh()
236 u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ + in dsi_mode_vrefresh()
237 timings->vback_porch.typ + timings->vsync_len.typ; in dsi_mode_vrefresh()
622 htotal = timings->hactive.typ + timings->hfront_porch.typ + in dw_mipi_dsi_line_timer_config()
623 timings->hback_porch.typ + timings->hsync_len.typ; in dw_mipi_dsi_line_timer_config()
625 hsa = timings->hback_porch.typ; in dw_mipi_dsi_line_timer_config()
626 hbp = timings->hsync_len.typ; in dw_mipi_dsi_line_timer_config()
647 vactive = timings->vactive.typ; in dw_mipi_dsi_vertical_timing_config()
648 vsa = timings->vback_porch.typ; in dw_mipi_dsi_vertical_timing_config()
[all …]
A Draydium-rm68200.c81 .pixelclock.typ = 54000000,
82 .hactive.typ = 720,
83 .hfront_porch.typ = 48,
84 .hback_porch.typ = 48,
85 .hsync_len.typ = 9,
86 .vactive.typ = 1280,
87 .vfront_porch.typ = 12,
88 .vback_porch.typ = 12,
89 .vsync_len.typ = 5,
A Ddw_hdmi.c465 hbl = edid->hback_porch.typ + edid->hfront_porch.typ + in hdmi_av_composer()
466 edid->hsync_len.typ; in hdmi_av_composer()
467 vbl = edid->vback_porch.typ + edid->vfront_porch.typ + in hdmi_av_composer()
468 edid->vsync_len.typ; in hdmi_av_composer()
496 hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1); in hdmi_av_composer()
497 hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0); in hdmi_av_composer()
500 hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1); in hdmi_av_composer()
501 hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0); in hdmi_av_composer()
987 edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ); in dw_hdmi_enable()
991 ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); in dw_hdmi_enable()
[all …]
A Dtegra.c115 writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width); in update_display_mode()
116 writel(dt->hback_porch.typ | dt->vback_porch.typ << 16, in update_display_mode()
118 writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16, in update_display_mode()
120 writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); in update_display_mode()
370 priv->width = timing->hactive.typ; in tegra_lcd_of_to_plat()
371 priv->height = timing->vactive.typ; in tegra_lcd_of_to_plat()
372 priv->pixel_clock = timing->pixelclock.typ; in tegra_lcd_of_to_plat()
A Dvideomodes.c452 timing->pixelclock.typ = mode->pixclock_khz * 1000; in video_ctfb_mode_to_display_timing()
454 timing->hactive.typ = mode->xres; in video_ctfb_mode_to_display_timing()
455 timing->hfront_porch.typ = mode->right_margin; in video_ctfb_mode_to_display_timing()
456 timing->hback_porch.typ = mode->left_margin; in video_ctfb_mode_to_display_timing()
457 timing->hsync_len.typ = mode->hsync_len; in video_ctfb_mode_to_display_timing()
459 timing->vactive.typ = mode->yres; in video_ctfb_mode_to_display_timing()
460 timing->vfront_porch.typ = mode->lower_margin; in video_ctfb_mode_to_display_timing()
461 timing->vback_porch.typ = mode->upper_margin; in video_ctfb_mode_to_display_timing()
462 timing->vsync_len.typ = mode->vsync_len; in video_ctfb_mode_to_display_timing()
A Dmvebu_lcd.c551 lcd_info.x_res = timings.hactive.typ; in mvebu_video_probe()
552 lcd_info.x_fp = timings.hfront_porch.typ; in mvebu_video_probe()
553 lcd_info.x_bp = timings.hback_porch.typ; in mvebu_video_probe()
554 lcd_info.y_res = timings.vactive.typ; in mvebu_video_probe()
555 lcd_info.y_fp = timings.vfront_porch.typ; in mvebu_video_probe()
556 lcd_info.y_bp = timings.vback_porch.typ; in mvebu_video_probe()
A Dihs_video_out.c261 timing.hactive.typ = 1024; in ihs_video_out_probe()
262 timing.vactive.typ = 768; in ihs_video_out_probe()
267 timing.hactive.typ = 720; in ihs_video_out_probe()
268 timing.vactive.typ = 400; in ihs_video_out_probe()
273 timing.hactive.typ = 640; in ihs_video_out_probe()
274 timing.vactive.typ = 480; in ihs_video_out_probe()
/u-boot/drivers/video/ti/
A Dtilcdc.c198 if (timing.pixelclock.typ > (LCDC_FMAX / 2)) { in tilcdc_probe()
200 timing.pixelclock.typ); in tilcdc_probe()
204 if (timing.hactive.typ > LCDC_MAX_WIDTH) in tilcdc_probe()
205 timing.hactive.typ = LCDC_MAX_WIDTH; in tilcdc_probe()
207 if (timing.vactive.typ > LCDC_MAX_HEIGHT) in tilcdc_probe()
208 timing.vactive.typ = LCDC_MAX_HEIGHT; in tilcdc_probe()
292 reg = (timing.hactive.typ * timing.vactive.typ * info.bpp) >> 3; in tilcdc_probe()
335 LCDC_RASTER_TIMING_2_HSWMSB(timing.hsync_len.typ) | in tilcdc_probe()
336 LCDC_RASTER_TIMING_2_VERMSB(timing.vactive.typ) | in tilcdc_probe()
374 uc_priv->xsize = timing.hactive.typ; in tilcdc_probe()
[all …]
A Dtilcdc-panel.c140 priv->timing.hactive.typ, priv->timing.vactive.typ, in tilcdc_panel_of_to_plat()
141 priv->info.bpp, priv->timing.pixelclock.typ); in tilcdc_panel_of_to_plat()
143 priv->timing.hback_porch.typ, priv->timing.hfront_porch.typ, in tilcdc_panel_of_to_plat()
144 priv->timing.hsync_len.typ); in tilcdc_panel_of_to_plat()
146 priv->timing.vback_porch.typ, priv->timing.vfront_porch.typ, in tilcdc_panel_of_to_plat()
147 priv->timing.vsync_len.typ); in tilcdc_panel_of_to_plat()
/u-boot/drivers/video/rockchip/
A Drk_vop.c44 u32 hactive = edid->hactive.typ; in rkvop_enable()
45 u32 vactive = edid->vactive.typ; in rkvop_enable()
50 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | in rkvop_enable()
51 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), in rkvop_enable()
150 u32 hactive = edid->hactive.typ; in rkvop_mode_set()
151 u32 vactive = edid->vactive.typ; in rkvop_mode_set()
152 u32 hsync_len = edid->hsync_len.typ; in rkvop_mode_set()
153 u32 hback_porch = edid->hback_porch.typ; in rkvop_mode_set()
154 u32 vsync_len = edid->vsync_len.typ; in rkvop_mode_set()
341 uc_priv->xsize = timing.hactive.typ; in rk_display_init()
[all …]
A Drk_mipi.c90 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); in rk_mipi_dsi_enable()
91 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); in rk_mipi_dsi_enable()
92 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ in rk_mipi_dsi_enable()
93 + timing->hback_porch.typ + timing->hactive.typ in rk_mipi_dsi_enable()
94 + timing->hfront_porch.typ)); in rk_mipi_dsi_enable()
95 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); in rk_mipi_dsi_enable()
96 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); in rk_mipi_dsi_enable()
97 rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ); in rk_mipi_dsi_enable()
98 rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ); in rk_mipi_dsi_enable()
/u-boot/drivers/video/meson/
A Dmeson_venc.c703 if (mode->hactive.typ < 640 || mode->hactive.typ > 1920) in meson_venc_hdmi_supported_mode()
706 if (mode->vactive.typ < 480 || mode->vactive.typ > 1200) in meson_venc_hdmi_supported_mode()
727 mode->hsync_len.typ; in meson_venc_hdmi_get_dmt_vmode()
730 mode->hactive.typ - 1; in meson_venc_hdmi_get_dmt_vmode()
822 total_pixels_venc = mode->hback_porch.typ + mode->hactive.typ + in meson_venc_hdmi_mode_set()
823 mode->hfront_porch.typ + mode->hsync_len.typ; in meson_venc_hdmi_mode_set()
959 lines_f0 = mode->vback_porch.typ + mode->vactive.typ + in meson_venc_hdmi_mode_set()
960 mode->vback_porch.typ + mode->vsync_len.typ; in meson_venc_hdmi_mode_set()
1245 mode->vactive.typ + in meson_venc_hdmi_mode_set()
1284 mode->vactive.typ + in meson_venc_hdmi_mode_set()
[all …]
A Dmeson_dw_hdmi.c199 timing.hactive.typ, timing.hfront_porch.typ, in meson_dw_hdmi_read_edid()
200 timing.hback_porch.typ, timing.hsync_len.typ, in meson_dw_hdmi_read_edid()
201 timing.vactive.typ, timing.vfront_porch.typ, in meson_dw_hdmi_read_edid()
202 timing.vback_porch.typ, timing.vsync_len.typ); in meson_dw_hdmi_read_edid()
/u-boot/drivers/video/stm32/
A Dstm32_ltdc.c225 hsync = timings->hsync_len.typ - 1; in stm32_ltdc_set_mode()
226 vsync = timings->vsync_len.typ - 1; in stm32_ltdc_set_mode()
227 acc_hbp = hsync + timings->hback_porch.typ; in stm32_ltdc_set_mode()
228 acc_vbp = vsync + timings->vback_porch.typ; in stm32_ltdc_set_mode()
229 acc_act_w = acc_hbp + timings->hactive.typ; in stm32_ltdc_set_mode()
382 timings.pixelclock.typ); in stm32_ltdc_probe()
416 priv->crop_w = timings.hactive.typ; in stm32_ltdc_probe()
417 priv->crop_h = timings.vactive.typ; in stm32_ltdc_probe()
421 timings.hactive.typ, timings.vactive.typ, in stm32_ltdc_probe()
432 uc_priv->xsize = timings.hactive.typ; in stm32_ltdc_probe()
[all …]
/u-boot/test/dm/
A Dtest-fdt.c1167 ut_assert(timing.hactive.typ == 240); in dm_test_decode_display_timing()
1170 ut_assert(timing.hsync_len.typ == 1); in dm_test_decode_display_timing()
1171 ut_assert(timing.vactive.typ == 320); in dm_test_decode_display_timing()
1174 ut_assert(timing.vsync_len.typ == 2); in dm_test_decode_display_timing()
1189 ut_assert(timing.hactive.typ == 480); in dm_test_decode_display_timing()
1192 ut_assert(timing.hsync_len.typ == 12); in dm_test_decode_display_timing()
1193 ut_assert(timing.vactive.typ == 800); in dm_test_decode_display_timing()
1196 ut_assert(timing.vsync_len.typ == 16); in dm_test_decode_display_timing()
1211 ut_assert(timing.hactive.typ == 800); in dm_test_decode_display_timing()
1214 ut_assert(timing.hsync_len.typ == 11); in dm_test_decode_display_timing()
[all …]

Completed in 42 milliseconds

12