Searched refs:u_int32_t (Results 1 – 8 of 8) sorted by relevance
10 u_int32_t pid12;11 u_int32_t emumgt;12 u_int32_t na1;13 u_int32_t na2;14 u_int32_t tim12;15 u_int32_t tim34;16 u_int32_t prd12;17 u_int32_t prd34;18 u_int32_t tcr;19 u_int32_t tgcr;[all …]
72 u_int32_t max_rx_len; /* Maximum receive packet length. */73 u_int32_t ctl; /* Control bitfield */145 #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)146 #define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
149 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; in nand_davinci_hwcontrol()167 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd) in nand_davinci_readecc()169 u_int32_t ecc = 0; in nand_davinci_readecc()179 u_int32_t val; in nand_davinci_enable_hwecc()193 u_int32_t tmp; in nand_davinci_calculate_ecc()228 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | in nand_davinci_correct_data()230 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) | in nand_davinci_correct_data()232 u_int32_t diff = ecc_calc ^ ecc_nand; in nand_davinci_correct_data()
52 u_int32_t next; /* Pointer to next descriptor55 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */56 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
153 u_int32_t clkdiv; in davinci_eth_mdio_enable()174 u_int32_t phy_act_state; in davinci_eth_phy_detect()421 u_int32_t clkdiv, cnt, mac_control; in davinci_emac_start()477 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); in davinci_emac_start()536 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); in davinci_emac_start()760 u_int32_t phy_id; in davinci_emac_probe()
68 (u_int32_t)di->cookie); in dev_enum_net()
264 (u_int32_t)di->cookie); in dev_enum_stor()
100 typedef __u32 u_int32_t; typedef
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