Home
last modified time | relevance | path

Searched refs:uint32_t (Results 1 – 25 of 695) sorted by relevance

12345678910>>...28

/u-boot/drivers/ram/k3-j721e/
A Dlpddr4_ctl_regs.h23 volatile uint32_t DENALI_CTL_0;
24 volatile uint32_t DENALI_CTL_1;
25 volatile uint32_t DENALI_CTL_2;
26 volatile uint32_t DENALI_CTL_3;
27 volatile uint32_t DENALI_CTL_4;
28 volatile uint32_t DENALI_CTL_5;
29 volatile uint32_t DENALI_CTL_6;
30 volatile uint32_t DENALI_CTL_7;
31 volatile uint32_t DENALI_CTL_8;
32 volatile uint32_t DENALI_CTL_9;
[all …]
A Dlpddr4_obj_if.h62 uint32_t (*start)(const lpddr4_privatedata* pd);
73 …uint32_t (*readreg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_…
84 …uint32_t (*writereg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32…
95 …uint32_t (*getmmrregister)(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrval…
105 …uint32_t (*setmmrregister)(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwsta…
209 uint32_t (*getphyindepinterruptmask)(const lpddr4_privatedata* pd, uint32_t* mask);
218 uint32_t (*setphyindepinterruptmask)(const lpddr4_privatedata* pd, const uint32_t* mask);
260 …uint32_t (*getlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupp…
353 …uint32_t (*getrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t*…
363 …uint32_t (*setrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uin…
[all …]
A Dcps_drv_lpddr4.h31 #define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg)))
51 (uint32_t)(CPS_FLD_SHIFT(fld)), \
52 (uint32_t)(reg_value)))
64 (uint32_t)(reg_value), (uint32_t)(value)))
74 (uint32_t)(CPS_FLD_MASK(fld)), \
75 (uint32_t)(CPS_FLD_WOCLR(fld)), \
76 (uint32_t)(reg_value)))
78 static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value) in cps_fldread()
93 static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t val… in cps_fldwrite()
109 static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_va… in cps_fldset()
[all …]
A Dlpddr4_if.h269 uint32_t lpddr4_start(const lpddr4_privatedata* pd);
280 uint32_t lpddr4_readreg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint…
291 uint32_t lpddr4_writereg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uin…
302 uint32_t lpddr4_getmmrregister(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmr…
312 uint32_t lpddr4_setmmrregister(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrw…
416 uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata* pd, uint32_t* mask);
425 uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata* pd, const uint32_t* mask);
466 uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwake…
557 uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32…
567 uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const …
[all …]
A Dlpddr4.c176 uint32_t result; in lpddr4_probe()
268 uint32_t regoffset, uint32_t * regvalue) in lpddr4_readreg()
313 uint32_t regoffset, uint32_t regvalue) in lpddr4_writereg()
361 uint32_t result = (uint32_t) CDN_EOK; in lpddr4_checkmmrreaderror()
427 uint32_t result = (uint32_t) CDN_EOK; in lpddr4_writemmrregister()
710 fieldshift = (uint32_t) intr - ((uint32_t) WORD_SHIFT); in lpddr4_checkctlinterrupt()
737 uint32_t localinterrupt = (uint32_t) intr; in lpddr4_ackctlinterrupt()
836 uint32_t ui32shiftinterrupt = (uint32_t) intr; in lpddr4_ackphyindepinterrupt()
859 uint32_t snum; in lpddr4_checkcatrainingerror()
890 uint32_t snum; in lpddr4_checkwrlvlerror()
[all …]
A Dlpddr4_private.h38 #define PI_OFFSET (((uint32_t)1) << 11)
39 #define PHY_OFFSET (((uint32_t)1) << 12)
46 #define IO_CALIB_DONE ((uint32_t)0x1U << 23U)
47 #define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U)
48 #define IO_CALIB_STATE ((uint32_t)0xBU << 28U)
49 #define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U)
51 ((uint32_t)LPDDR4_BIT_MASK << 4U))
52 #define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U)
54 ((uint32_t)LPDDR4_BIT_MASK << 6U))
56 (((uint32_t)BYTE_MASK) << 16U))
[all …]
/u-boot/arch/arm/include/asm/arch-aspeed/
A Dscu_ast2600.h169 uint32_t hpll; /* 0x200 */
172 uint32_t apll; /* 0x210 */
175 uint32_t mpll; /* 0x220 */
178 uint32_t epll; /* 0x240 */
181 uint32_t dpll; /* 0x260 */
184 uint32_t clksrc1; /* 0x300 */
185 uint32_t clksrc2; /* 0x304 */
186 uint32_t clksrc3; /* 0x308 */
188 uint32_t clksrc4; /* 0x310 */
189 uint32_t clksrc5; /* 0x314 */
[all …]
/u-boot/arch/arm/include/asm/arch-mxs/
A Dregs-digctl.h22 uint32_t reserved_writeonce[3];
26 uint32_t reserved_entropy[3];
28 uint32_t reserved_entropy_latched[3];
30 uint32_t reserved1[4];
34 uint32_t reserved_hw_digctl_dbgrd[3];
36 uint32_t reserved_hw_digctl_dbg[3];
38 uint32_t reserved2[4];
56 uint32_t reserved3[36];
78 uint32_t reserved4[4];
83 uint32_t reserved5[12];
[all …]
A Dregs-usb.h13 uint32_t hw_usbctrl_id; /* 0x000 */
15 uint32_t hw_usbctrl_hwhost; /* 0x008 */
20 uint32_t reserved1[26];
28 uint32_t reserved2[27];
34 uint32_t reserved3[5];
39 uint32_t reserved4[6];
46 uint32_t reserved5;
61 uint32_t reserved6;
66 uint32_t reserved7;
71 uint32_t reserved8;
[all …]
/u-boot/drivers/net/
A Dfec_mxc.h26 uint32_t res0[1]; /* MBAR_ETH + 0x000 */
27 uint32_t ievent; /* MBAR_ETH + 0x004 */
28 uint32_t imask; /* MBAR_ETH + 0x008 */
30 uint32_t res1[1]; /* MBAR_ETH + 0x00C */
34 uint32_t ecntrl; /* MBAR_ETH + 0x024 */
47 uint32_t paddr1; /* MBAR_ETH + 0x0E4 */
48 uint32_t paddr2; /* MBAR_ETH + 0x0E8 */
52 uint32_t iaddr1; /* MBAR_ETH + 0x118 */
53 uint32_t iaddr2; /* MBAR_ETH + 0x11C */
263 uint32_t reset_delay;
[all …]
/u-boot/arch/arm/include/asm/arch-ep93xx/
A Dep93xx.h38 uint32_t status;
40 uint32_t remain;
43 uint32_t base0;
47 uint32_t base1;
80 uint32_t badd;
82 uint32_t blen;
107 uint32_t gt;
108 uint32_t fct;
109 uint32_t fcf;
110 uint32_t afp;
[all …]
/u-boot/include/
A Dimx_lpi2c.h114 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIF…
117 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIF…
126 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIF…
129 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIF…
134 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIF…
137 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIF…
140 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIF…
143 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIF…
146 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIF…
149 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIF…
[all …]
A Dpe.h49 uint32_t Size;
58 uint32_t SizeOfCode;
62 uint32_t BaseOfCode;
73 uint32_t SizeOfImage;
75 uint32_t CheckSum;
88 uint32_t Signature;
100 uint32_t SizeOfCode;
104 uint32_t BaseOfCode;
105 uint32_t BaseOfData;
109 uint32_t ImageBase;
[all …]
A Dimximage.h122 uint32_t dcd_ptr;
137 uint32_t addr;
138 uint32_t value;
165 uint32_t start;
166 uint32_t size;
167 uint32_t plugin;
172 uint32_t entry;
174 uint32_t dcd_ptr;
176 uint32_t self;
177 uint32_t csf;
[all …]
/u-boot/arch/arm/include/asm/arch-pxa/
A Dregs-usb.h13 uint32_t udccr; /* 0x000 */
14 uint32_t reserved1;
18 uint32_t reserved2;
41 uint32_t reserved3[7];
43 uint32_t reserved4[7];
45 uint32_t reserved5[7];
47 uint32_t reserved6[7];
49 uint32_t reserved7[31];
51 uint32_t reserved8[31];
53 uint32_t reserved9[127];
[all …]
/u-boot/arch/arm/include/asm/ti-common/
A Ddavinci_nand.h32 uint32_t ercsr;
33 uint32_t awccr;
34 uint32_t sdbcr;
35 uint32_t sdrcr;
46 uint32_t ddrsr;
49 uint32_t totar;
53 uint32_t eirr;
54 uint32_t eimr;
55 uint32_t eimsr;
56 uint32_t eimcr;
[all …]
/u-boot/arch/arm/include/asm/arch-mx7/
A Dcrm_regs.h24 uint32_t ccgr;
25 uint32_t ccgr_set;
26 uint32_t ccgr_clr;
27 uint32_t ccgr_tog;
31 uint32_t target_root;
36 uint32_t post;
40 uint32_t pre;
53 uint32_t gpr0;
54 uint32_t gpr0_set;
55 uint32_t gpr0_clr;
[all …]
/u-boot/tools/
A Dzynqmpimage.h36 uint32_t address;
37 uint32_t data;
44 uint32_t version; /* 0x00 */
45 uint32_t nr_parts; /* 0x04 */
49 uint32_t boot_device; /* 0x14 */
51 uint32_t checksum; /* 0x3c */
112 uint32_t checksum; /* 0x3c */
119 uint32_t encryption; /* 0x28 */
120 uint32_t image_load; /* 0x2c */
124 uint32_t image_size; /* 0x3c */
[all …]
A Dmxsimage.h95 uint32_t header;
96 uint32_t entry;
98 uint32_t dcd;
100 uint32_t self;
101 uint32_t csf;
117 uint32_t ret = 0; in sb_hab_ivt_header()
159 uint32_t count;
160 uint32_t crc32;
164 uint32_t count;
182 uint32_t mode;
[all …]
A Dmtk_image.h18 uint32_t version;
19 uint32_t size;
57 uint32_t version;
60 uint32_t magic;
61 uint32_t type;
64 uint32_t unused;
109 uint32_t unused;
132 uint32_t attr;
144 uint32_t pad;
172 uint32_t pad;
[all …]
/u-boot/arch/arm/include/asm/
A Darmv7m.h27 uint32_t cpuid; /* CPUID Base Register */
28 uint32_t icsr; /* Interrupt Control and State Register */
29 uint32_t vtor; /* Vector Table Offset Register */
31 uint32_t scr; /* offset 0x10: System Control Register */
39 uint32_t res; /* offset 0x30: reserved */
41 uint32_t bfar; /* offset 0x38: BusFault Address Reg */
59 uint32_t type; /* Type Register */
60 uint32_t ctrl; /* Control Register */
61 uint32_t rnr; /* Region Number Register */
62 uint32_t rbar; /* Region Base Address Register */
[all …]
/u-boot/arch/x86/include/asm/arch-quark/
A Dmrc.h63 uint32_t ras;
64 uint32_t wtr;
65 uint32_t rrd;
66 uint32_t faw;
82 uint32_t scrambler_seed;
118 uint32_t rank_enables;
122 uint32_t address_mode;
140 uint32_t menu_after_mrc;
142 uint32_t tune_rcvn;
150 uint32_t status;
[all …]
/u-boot/arch/arm/include/asm/arch-tegra/
A Dbpmp_abi.h78 uint32_t mrq;
80 uint32_t flags;
98 uint32_t flags;
250 uint32_t addr;
289 uint32_t size;
300 uint32_t base;
326 uint32_t base;
353 uint32_t clr;
355 uint32_t set;
426 uint32_t eof;
[all …]
/u-boot/board/esd/vme8349/
A Dcaddy.h32 uint32_t cmd;
33 uint32_t issue;
34 uint32_t addr;
35 uint32_t par[5];
39 uint32_t answer;
40 uint32_t issue;
41 uint32_t status;
42 uint32_t par[5];
47 uint32_t cmd_in;
48 uint32_t cmd_out;
[all …]
/u-boot/arch/x86/include/asm/arch-ivybridge/
A Dpei_data.h27 uint32_t pei_version;
28 uint32_t mchbar;
29 uint32_t dmibar;
30 uint32_t epbar;
31 uint32_t pciexbar;
33 uint32_t wdbbar;
34 uint32_t wdbsize;
36 uint32_t rcba;
37 uint32_t pmbase;
38 uint32_t gpiobase;
[all …]

Completed in 117 milliseconds

12345678910>>...28