| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| A D | serial_scc.c | 125 up->scc_maxidl = 0; in mpc85xx_serial_init()
126 up->scc_brkcr = 1; in mpc85xx_serial_init()
127 up->scc_parec = 0; in mpc85xx_serial_init()
128 up->scc_frmec = 0; in mpc85xx_serial_init()
129 up->scc_nosec = 0; in mpc85xx_serial_init()
130 up->scc_brkec = 0; in mpc85xx_serial_init()
131 up->scc_uaddr1 = 0; in mpc85xx_serial_init()
132 up->scc_uaddr2 = 0; in mpc85xx_serial_init()
133 up->scc_toseq = 0; in mpc85xx_serial_init()
134 up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; in mpc85xx_serial_init()
[all …]
|
| A D | mp.c | 336 u32 up, cpu_up_mask, whoami; in plat_mp_up() local
357 up = ((1 << cpu_numcores()) - 1); in plat_mp_up()
359 bpcr |= (up << 24); in plat_mp_up()
372 if ((cpu_up_mask & up) == up) in plat_mp_up()
381 cpu_up_mask, up); in plat_mp_up()
|
| /u-boot/arch/arm/dts/ |
| A D | imx28.dtsi | 226 fsl,pull-up = <MXS_PULL_DISABLE>;
237 fsl,pull-up = <MXS_PULL_DISABLE>;
250 fsl,pull-up = <MXS_PULL_DISABLE>;
274 fsl,pull-up = <MXS_PULL_DISABLE>;
297 fsl,pull-up = <MXS_PULL_DISABLE>;
308 fsl,pull-up = <MXS_PULL_DISABLE>;
442 fsl,pull-up = <MXS_PULL_ENABLE>;
468 fsl,pull-up = <MXS_PULL_ENABLE>;
483 fsl,pull-up = <MXS_PULL_ENABLE>;
503 fsl,pull-up = <MXS_PULL_ENABLE>;
[all …]
|
| A D | sama7g5ek.dts | 125 bias-pull-up;
138 bias-pull-up;
146 bias-pull-up;
155 bias-pull-up;
163 bias-pull-up;
186 bias-pull-up;
|
| A D | imx23.dtsi | 152 fsl,pull-up = <MXS_PULL_DISABLE>;
165 fsl,pull-up = <MXS_PULL_DISABLE>;
176 fsl,pull-up = <MXS_PULL_DISABLE>;
187 fsl,pull-up = <MXS_PULL_DISABLE>;
213 fsl,pull-up = <MXS_PULL_DISABLE>;
238 fsl,pull-up = <MXS_PULL_ENABLE>;
258 fsl,pull-up = <MXS_PULL_ENABLE>;
290 fsl,pull-up = <MXS_PULL_ENABLE>;
309 fsl,pull-up = <MXS_PULL_ENABLE>;
369 fsl,pull-up = <MXS_PULL_ENABLE>;
[all …]
|
| A D | s700-cubieboard7.dts | 59 bias-pull-up;
70 bias-pull-up;
81 bias-pull-up;
|
| A D | zynq-zc702.dts | 45 linux,code = <103>; /* up */
277 conf-pull-up {
279 bias-pull-up;
296 bias-pull-up;
336 bias-pull-up;
349 bias-pull-up;
|
| A D | zynq-zc706.dts | 194 conf-pull-up {
196 bias-pull-up;
213 bias-pull-up;
240 bias-pull-up;
253 bias-pull-up;
|
| /u-boot/drivers/serial/ |
| A D | serial_mpc8xx.c | 85 smc_uart_t __iomem *up; in serial_mpc8xx_probe() local
92 up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC]; in serial_mpc8xx_probe()
94 out_be16(&up->smc_rpbase, 0); in serial_mpc8xx_probe()
130 out_be16(&up->smc_rbase, CPM_SERIAL_BASE); in serial_mpc8xx_probe()
131 out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t)); in serial_mpc8xx_probe()
132 out_8(&up->smc_rfcr, SMC_EB); in serial_mpc8xx_probe()
133 out_8(&up->smc_tfcr, SMC_EB); in serial_mpc8xx_probe()
153 out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN); in serial_mpc8xx_probe()
154 out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE); in serial_mpc8xx_probe()
|
| /u-boot/doc/device-tree-bindings/rtc/ |
| A D | brcm,brcmstb-waketimer.txt | 1 Broadcom STB wake-up Timer
3 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
4 ability to wake up the system from low-power suspend/standby modes.
|
| /u-boot/arch/arm/mach-imx/ |
| A D | imx_bootaux.c | 107 int ret, up; in do_bootaux() local
112 up = arch_auxiliary_core_check_up(0); in do_bootaux()
113 if (up) { in do_bootaux()
|
| /u-boot/board/freescale/ls1021aiot/ |
| A D | ls102xa_rcw_sd.cfg | 11 #SATA set-up
17 #HDMI set-up
|
| /u-boot/board/udoo/ |
| A D | README | 20 - Insert the SD card in the board, power it up and U-Boot messages should
21 come up.
|
| /u-boot/arch/x86/cpu/ |
| A D | u-boot-spl.lds | 48 * Force 32-byte alignment so that it lines up with the start of
49 * bss, which may have up to 32-byte alignment. This ensures
50 * that the end of the .bin file matches up with
|
| /u-boot/doc/board/google/ |
| A D | chromebook_coral.rst | 26 sets up some SDRAM at ffff8000 and loads the TPL image to that address. The
27 SRAM extends up to the top of 32-bit address space, but the last 2KB is the
34 TPL (running from start.S) first sets up CAR (Cache-as-RAM) which provides
36 (fef00000) and is 768KB in size. It then sets up the stack in the botttom 64KB
49 TPL does not set up a bloblist since at present it does not have anything to
66 It calls arch_cpu_init_spl() to set up a few devices, then init_dram() loads
67 the FSP-M binary into CAR and runs to, to set up SDRAM. The address of the
74 up by TPL is still active.
104 up by TPL is still active until relocation.
138 platforms start up (those that don't use SPL).
[all …]
|
| A D | chromebook_link.rst | 11 * mrc.bin - Memory Reference Code, which sets up SDRAM
12 * video ROM - sets up the display
|
| /u-boot/board/solidrun/mx6cuboxi/ |
| A D | README | 20 - Insert the SD card in the board, power it up and U-Boot messages should
21 come up.
|
| /u-boot/board/freescale/ls1021aqds/ |
| A D | README | 15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
22 up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
37 supporting speeds up to 1600Mtps
45 - Two PCI Express Gen2 controllers running at up to 5 GHz
59 - Four GPIO controllers supporting up to 109 general purpose I/O signals
65 - IPSec forwarding at up to 1Gbps
80 - Supports rates of up to 1600 MHz data-rate
|
| /u-boot/board/freescale/ls1021atwr/ |
| A D | README | 15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
22 up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
37 supporting speeds up to 1600Mtps
45 - Two PCI Express Gen2 controllers running at up to 5 GHz
59 - Four GPIO controllers supporting up to 109 general purpose I/O signals
65 - IPSec forwarding at up to 1Gbps
80 - Supports rates of up to 1600 MHz data-rate
|
| /u-boot/board/phytec/pcl063/ |
| A D | README | 24 - Insert the micro SD card in the board and power it up.
26 - U-Boot messages should come up.
|
| /u-boot/board/freescale/ls1043ardb/ |
| A D | README | 22 - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
30 - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
33 - Two 4-pin serial ports at up to 115.2 Kbit/s
|
| /u-boot/board/engicam/imx6ul/ |
| A D | README | 32 - Insert the micro SD card in the board, power it up and U-Boot messages should
33 come up.
|
| /u-boot/board/freescale/ls2080aqds/ |
| A D | README | 25 chip-selects and two DIMM connectors. Support is up to 2133MT/s.
27 and two DIMM connectors. Support is up to 1600MT/s.
46 - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
47 - 8 MB high-speed flash Memory (up to 104 MHz)
48 - 512 MB low-speed flash Memory (up to 40 MHz)
53 - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
142 - Card can operate with up to 4 QSGMII lane simultaneously
143 - Card can operate with up to 8 SGMII lane simultaneously
|
| /u-boot/arch/mips/include/asm/ |
| A D | sgidefs.h | 15 #error Use a Linux compiler or give up.
|
| /u-boot/doc/ |
| A D | README.mpc85xx-spin-table | 9 Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
20 TLB. While booting, they set up another TLB in AS=1 space and jump into
|