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/u-boot/arch/arm/include/asm/arch-mx5/
A Dcrm_regs.h80 #define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) argument
92 #define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) argument
109 #define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) argument
116 #define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) argument
122 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) argument
134 #define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13) argument
138 #define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10) argument
142 #define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8) argument
154 #define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7) argument
333 #define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) argument
[all …]
/u-boot/arch/arm/include/asm/arch-vf610/
A Dimx-regs.h132 #define DDRMC_CR10_TRST_PWRON(v) (v) argument
133 #define DDRMC_CR11_CKE_INACTIVE(v) (v) argument
147 #define DDRMC_CR17_TMOD(v) ((v) & 0xff) argument
149 #define DDRMC_CR18_TCKE(v) ((v) & 0x7) argument
156 #define DDRMC_CR23_TDLL(v) ((v) & 0xffff) argument
157 #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) argument
160 #define DDRMC_CR26_TRFC(v) ((v) & 0x3ff) argument
165 #define DDRMC_CR31_TXSR(v) ((v) & 0xffff) argument
178 #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) argument
180 #define DDRMC_CR70_REF_PER_ZQ(v) (v) argument
[all …]
A Dcrm_regs.h118 #define CCM_CCR_OSCNT(v) ((v) & 0xff) argument
137 #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) argument
138 #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) argument
142 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) argument
146 #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) argument
149 #define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) argument
152 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) argument
183 #define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20) argument
192 #define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) argument
193 #define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) argument
[all …]
/u-boot/arch/powerpc/include/asm/
A Datomic.h16 #define atomic_read(v) ((v)->counter) argument
17 #define atomic_set(v,i) (((v)->counter) = (i)) argument
32 : "r" (a), "r" (v), "m" (*v) in atomic_add_return()
48 : "r" (a), "r" (v), "m" (*v) in atomic_sub_return()
64 : "r" (v), "m" (*v) in atomic_inc_return()
80 : "r" (v), "m" (*v) in atomic_dec_return()
86 #define atomic_add(a, v) ((void) atomic_add_return((a), (v))) argument
87 #define atomic_sub(a, v) ((void) atomic_sub_return((a), (v))) argument
89 #define atomic_inc(v) ((void) atomic_inc_return((v))) argument
90 #define atomic_dec(v) ((void) atomic_dec_return((v))) argument
[all …]
/u-boot/include/asm-generic/
A Datomic-long.h31 return (long)atomic64_read(v); in atomic_long_read()
38 atomic64_set(v, i); in atomic_long_set()
45 atomic64_inc(v); in atomic_long_inc()
52 atomic64_dec(v); in atomic_long_dec()
59 atomic64_add(i, v); in atomic_long_add()
66 atomic64_sub(i, v); in atomic_long_sub()
157 atomic_set(v, i); in atomic_long_set()
164 atomic_inc(v); in atomic_long_inc()
171 atomic_dec(v); in atomic_long_dec()
178 atomic_add(i, v); in atomic_long_add()
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A Datomic.h15 #define atomic_read(v) ((v)->counter) argument
16 #define atomic_set(v, i) ((v)->counter = (i)) argument
17 #define atomic64_read(v) atomic_read(v) argument
18 #define atomic64_set(v, i) atomic_set(v, i) argument
25 v->counter += i; in atomic_add()
34 v->counter -= i; in atomic_sub()
43 ++v->counter; in atomic_inc()
52 --v->counter; in atomic_dec()
62 val = v->counter; in atomic_dec_and_test()
98 v->counter += i; in atomic64_add()
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/u-boot/arch/arm/include/asm/arch-s32v234/
A Dsiul.h78 #define SIUL2_MSCR_OBE(v) ((v) & 0x00200000) argument
81 #define SIUL2_MSCR_ODE(v) ((v) & 0x00100000) argument
84 #define SIUL2_MSCR_IBE(v) ((v) & 0x00010000) argument
87 #define SIUL2_MSCR_HYS(v) ((v) & 0x00400000) argument
90 #define SIUL2_MSCR_INV(v) ((v) & 0x00020000) argument
93 #define SIUL2_MSCR_PKE(v) ((v) & 0x00010000) argument
96 #define SIUL2_MSCR_SRE(v) ((v) & 0x0000C000) argument
102 #define SIUL2_MSCR_PUE(v) ((v) & 0x00002000) argument
105 #define SIUL2_MSCR_PUS(v) ((v) & 0x00001800) argument
111 #define SIUL2_MSCR_DSE(v) ((v) & 0x00000700) argument
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/u-boot/drivers/usb/host/
A Dehci-mxc.c67 unsigned int v; in mxc_set_usbcontrol() local
78 v |= MX25_OTG_PM_BIT; in mxc_set_usbcontrol()
81 v |= MX25_OTG_PP_BIT; in mxc_set_usbcontrol()
95 v |= MX25_H1_PM_BIT; in mxc_set_usbcontrol()
98 v |= MX25_H1_PP_BIT; in mxc_set_usbcontrol()
104 v |= MX25_H1_TLL_BIT; in mxc_set_usbcontrol()
134 v |= MX31_H1_PM_BIT; in mxc_set_usbcontrol()
137 v |= MX31_H1_DT_BIT; in mxc_set_usbcontrol()
145 v |= MX31_H2_PM_BIT; in mxc_set_usbcontrol()
148 v |= MX31_H2_DT_BIT; in mxc_set_usbcontrol()
[all …]
A Dehci-mx5.c86 unsigned int v; in mxc_set_usbcontrol() local
96 v = __raw_readl(usbother_base + in mxc_set_usbcontrol()
99 v |= MXC_OTG_PHYCTRL_OC_POL_BIT; in mxc_set_usbcontrol()
107 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; in mxc_set_usbcontrol()
114 __raw_writel(v, usbother_base + in mxc_set_usbcontrol()
120 v &= ~MXC_OTG_UCTRL_OPM_BIT; in mxc_set_usbcontrol()
122 v |= MXC_OTG_UCTRL_OPM_BIT; in mxc_set_usbcontrol()
159 v |= MXC_H1_OC_POL_BIT; in mxc_set_usbcontrol()
161 v &= ~MXC_H1_OC_POL_BIT; in mxc_set_usbcontrol()
179 v |= MXC_H2_UCTRL_H2_OC_POL_BIT; in mxc_set_usbcontrol()
[all …]
/u-boot/arch/x86/include/asm/
A Datomic.h24 static inline int atomic_read(const atomic_t *v) in atomic_read() argument
26 return READ_ONCE((v)->counter); in atomic_read()
38 v->counter = i; in atomic_set()
51 : "+m" (v->counter) in atomic_add()
65 : "+m" (v->counter) in atomic_sub()
75 static inline void atomic_inc(atomic_t *v) in atomic_inc() argument
78 : "+m" (v->counter)); in atomic_inc()
87 static inline void atomic_dec(atomic_t *v) in atomic_dec() argument
90 : "+m" (v->counter)); in atomic_dec()
102 asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v)); in atomic_inc_short()
[all …]
/u-boot/common/
A Ds_record.c88 switch (v) { in srec_decode()
94 *addr += v; in srec_decode()
95 chksum += v; in srec_decode()
104 *addr += v; in srec_decode()
105 chksum += v; in srec_decode()
116 *addr += v; in srec_decode()
117 chksum += v; in srec_decode()
124 *addr += v; in srec_decode()
125 chksum += v; in srec_decode()
138 data[i] = v; in srec_decode()
[all …]
/u-boot/arch/mips/mach-ath79/qca953x/
A Dlowlevel_init.S25 #define SET_FIELD(name, v) (((v) & QCA953X_##name##_MASK) << \ argument
28 #define DPLL2_KI(v) SET_FIELD(SRIF_DPLL2_KI, v) argument
29 #define DPLL2_KD(v) SET_FIELD(SRIF_DPLL2_KD, v) argument
33 #define PLL_CPU_NFRAC(v) SET_FIELD(PLL_CPU_CONFIG_NFRAC, v) argument
34 #define PLL_CPU_NINT(v) SET_FIELD(PLL_CPU_CONFIG_NINT, v) argument
35 #define PLL_CPU_REFDIV(v) SET_FIELD(PLL_CPU_CONFIG_REFDIV, v) argument
36 #define PLL_CPU_OUTDIV(v) SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v) argument
43 #define PLL_DDR_NFRAC(v) SET_FIELD(PLL_DDR_CONFIG_NFRAC, v) argument
44 #define PLL_DDR_NINT(v) SET_FIELD(PLL_DDR_CONFIG_NINT, v) argument
45 #define PLL_DDR_REFDIV(v) SET_FIELD(PLL_DDR_CONFIG_REFDIV, v) argument
[all …]
/u-boot/drivers/memory/
A Dti-aemif.c18 #define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) argument
19 #define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) argument
20 #define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26) argument
21 #define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20) argument
22 #define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17) argument
23 #define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13) argument
24 #define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7) argument
25 #define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4) argument
26 #define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2) argument
27 #define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0) argument
/u-boot/arch/arm/include/asm/arch-mx6/
A Dcrm_regs.h411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) argument
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) argument
417 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) argument
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) argument
424 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) argument
428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) argument
431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) argument
444 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
985 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ argument
1046 #define BF_ANADIG_PLL_528_RSVD1(v) \ argument
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/u-boot/arch/arc/include/asm/
A Dio.h86 #define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); }) argument
170 #define writeb_relaxed(v, c) ((void)__arch_putb((v), (c))) argument
192 #define writeb(v, c) ({ __iowmb(); writeb_relaxed(v, c); }) argument
193 #define writew(v, c) ({ __iowmb(); writew_relaxed(v, c); }) argument
194 #define writel(v, c) ({ __iowmb(); writel_relaxed(v, c); }) argument
195 #define writeq(v, c) ({ __iowmb(); writeq_relaxed(v, c); }) argument
200 #define out_le32(a, v) out_arch(l, le32, a, v) argument
201 #define out_le16(a, v) out_arch(w, le16, a, v) argument
206 #define out_be32(a, v) out_arch(l, be32, a, v) argument
207 #define out_be16(a, v) out_arch(w, be16, a, v) argument
[all …]
/u-boot/drivers/clk/
A Dclk_pic32.c98 ulong plliclk, v; in pic32_get_pll_rate() local
120 ulong v; in pic32_get_sysclk() local
177 u32 div, trim, v; in pic32_set_refclk() local
207 v = readl(reg); in pic32_set_refclk()
214 writel(v, reg); in pic32_set_refclk()
242 v = readl(reg); in pic32_get_refclk()
277 v = (u32)rate64; in pic32_get_refclk()
281 return v; in pic32_get_refclk()
286 u32 v, idiv, mul; in pic32_get_mpll_rate() local
291 idiv = v & MPLL_IDIV; in pic32_get_mpll_rate()
[all …]
/u-boot/drivers/pwm/
A Dsunxi_pwm.c73 u32 v, best_period = 0, duty; in sunxi_pwm_set_config() local
104 v = readl(&regs->ctrl); in sunxi_pwm_set_config()
106 writel(v, &regs->ctrl); in sunxi_pwm_set_config()
109 writel(v, &regs->ctrl); in sunxi_pwm_set_config()
110 v |= SUNXI_PWM_CTRL_CLK_GATE; in sunxi_pwm_set_config()
111 writel(v, &regs->ctrl); in sunxi_pwm_set_config()
129 u32 v; in sunxi_pwm_set_enable() local
133 v = readl(&regs->ctrl); in sunxi_pwm_set_enable()
136 writel(v, &regs->ctrl); in sunxi_pwm_set_enable()
146 v |= SUNXI_PWM_CTRL_ENABLE0; in sunxi_pwm_set_enable()
[all …]
/u-boot/scripts/kconfig/
A Dpreprocess.c242 return v; in variable_lookup()
254 if (!v) in variable_expand()
264 v->exp_count++; in variable_expand()
271 v->exp_count--; in variable_expand()
284 if (v) { in variable_add()
290 free(v->value); in variable_add()
297 v = xmalloc(sizeof(*v)); in variable_add()
311 v->value = xrealloc(v->value, in variable_add()
324 free(v->name); in variable_del()
325 free(v->value); in variable_del()
[all …]
/u-boot/arch/sh/cpu/sh4/
A Dcache.c60 u32 v; in flush_dcache_range() local
63 for (v = start; v < end; v += L1_CACHE_BYTES) { in flush_dcache_range()
65 : "m" (__m(v))); in flush_dcache_range()
71 u32 v; in invalidate_dcache_range() local
74 for (v = start; v < end; v += L1_CACHE_BYTES) { in invalidate_dcache_range()
76 : "m" (__m(v))); in invalidate_dcache_range()
/u-boot/drivers/clk/ti/
A Dclk-gate.c27 u32 v; in clk_ti_gate_disable() local
29 v = readl(priv->reg); in clk_ti_gate_disable()
31 v |= (1 << priv->enable_bit); in clk_ti_gate_disable()
33 v &= ~(1 << priv->enable_bit); in clk_ti_gate_disable()
35 writel(v, priv->reg); in clk_ti_gate_disable()
43 u32 v; in clk_ti_gate_enable() local
45 v = readl(priv->reg); in clk_ti_gate_enable()
47 v &= ~(1 << priv->enable_bit); in clk_ti_gate_enable()
49 v |= (1 << priv->enable_bit); in clk_ti_gate_enable()
51 writel(v, priv->reg); in clk_ti_gate_enable()
[all …]
/u-boot/tools/kermit/
A Ddot.kermrc13 define sz !sz \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
14 define rz !rz \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
15 define sx !sx \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
16 define rx !rx \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
/u-boot/include/
A Dfsl_sec.h16 #define sec_out32(a, v) out_le32(a, v) argument
22 #define sec_out32(a, v) out_be32(a, v) argument
284 #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v)) argument
286 #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v)) argument
289 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
292 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
298 #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4) argument
299 #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC) argument
300 #define SM_PERM(v) (v == 1 ? 0x10 : 0x4) argument
301 #define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8) argument
[all …]
/u-boot/arch/arm/include/asm/
A Dio.h98 #define __raw_writeb(v,a) __arch_putb(v,a) argument
99 #define __raw_writew(v,a) __arch_putw(v,a) argument
100 #define __raw_writel(v,a) __arch_putl(v,a) argument
101 #define __raw_writeq(v,a) __arch_putq(v,a) argument
175 #define out_le64(a,v) out_arch(q,le64,a,v) argument
176 #define out_le32(a,v) out_arch(l,le32,a,v) argument
177 #define out_le16(a,v) out_arch(w,le16,a,v) argument
191 #define out_64(a,v) __raw_writeq(v,a) argument
192 #define out_32(a,v) __raw_writel(v,a) argument
193 #define out_16(a,v) __raw_writew(v,a) argument
[all …]
/u-boot/drivers/bios_emulator/
A Dbiosemui.h71 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
72 #define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
73 writeb_le(base + 1, (v >> 8) & 0xff)
74 #define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
75 writeb_le(base + 1, (v >> 8) & 0xff), \
76 writeb_le(base + 2, (v >> 16) & 0xff), \
77 writeb_le(base + 3, (v >> 24) & 0xff)
82 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
83 #define writew_le(base, v) *((u16*)(base)) = (v) argument
84 #define writel_le(base, v) *((u32*)(base)) = (v) argument
/u-boot/arch/sh/include/asm/
A Dio.h37 #define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v)) argument
38 #define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v)) argument
39 #define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v)) argument
49 #define __raw_writeb(v, a) __arch_putb(v, a) argument
50 #define __raw_writew(v, a) __arch_putw(v, a) argument
51 #define __raw_writel(v, a) __arch_putl(v, a) argument
84 #define outb(v, p) __raw_writeb(v, p) argument
152 #define writeb(v, c) __raw_writeb(v, __mem_pci(c)) argument
185 #define writeb(v, addr) __raw_writeb(v, addr) argument
186 #define writew(v, addr) __raw_writew(v, addr) argument
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