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Searched refs:val_cfg0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mm.c390 u32 val_cfg0; in clock_init() local
399 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); in clock_init()
400 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
405 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); in clock_init()
407 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); in clock_init()
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | in clock_init()
413 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); in clock_init()
A Dclock_imx8mq.c659 u32 val_cfg0, val_cfg1, divq; in frac_pll_init() local
674 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | in frac_pll_init()
687 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); in frac_pll_init()
688 val_cfg0 = readl(pll_cfg0); in frac_pll_init()
691 ret = readl_poll_timeout(pll_cfg0, val_cfg0, in frac_pll_init()
692 val_cfg0 & FRAC_PLL_LOCK_MASK, 1); in frac_pll_init()

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