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Searched refs:where (Results 1 – 25 of 242) sorted by relevance

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/u-boot/drivers/pci/
A Dpci-rcar-gen3.c134 int shift = 8 * (where & 3); in rcar_rmw32()
136 clrsetbits_le32(priv->regs + (where & ~3), in rcar_rmw32()
143 int shift = 8 * (where & 3); in rcar_read_conf()
150 pci_dev_t bdf, int where, ulong *data) in rcar_pcie_config_access() argument
153 u32 reg = where & ~3; in rcar_pcie_config_access()
215 uint where, ulong *val, in rcar_gen3_pcie_read_config() argument
221 ret = rcar_gen3_pcie_addr_valid(bdf, where); in rcar_gen3_pcie_read_config()
228 bdf, where, &reg); in rcar_gen3_pcie_read_config()
238 uint where, ulong val, in rcar_gen3_pcie_write_config() argument
244 ret = rcar_gen3_pcie_addr_valid(bdf, where); in rcar_gen3_pcie_write_config()
[all …]
A Dpci_gt64120.c47 int where, u32 *data) in gt_config_access() argument
63 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data); in gt_config_access()
71 addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF; in gt_config_access()
112 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data); in gt_config_access()
118 int where, u32 *value) in gt_read_config_dword() argument
123 return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value); in gt_read_config_dword()
127 int where, u32 value) in gt_write_config_dword() argument
132 return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data); in gt_write_config_dword()
A Dpci_msc01.c30 int where, u32 *data) in msc01_config_access() argument
46 ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF), in msc01_config_access()
66 int where, u32 *value) in msc01_read_config_dword() argument
71 return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value); in msc01_read_config_dword()
75 int where, u32 value) in msc01_write_config_dword() argument
80 return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data); in msc01_write_config_dword()
A Dpcie_imx.c327 pci_dev_t d, int where) in get_bus_address() argument
346 va_address += (where & ~0x3); in get_bus_address()
392 int where, u32 *val) in imx_pcie_read_cfg() argument
403 va_address = get_bus_address(priv, d, where); in imx_pcie_read_cfg()
421 int where, u32 val) in imx_pcie_write_cfg() argument
430 va_address = get_bus_address(priv, d, where); in imx_pcie_write_cfg()
683 int where, u32 *val) in imx_pcie_read_config() argument
687 return imx_pcie_read_cfg(priv, d, where, val); in imx_pcie_read_config()
691 int where, u32 val) in imx_pcie_write_config() argument
695 return imx_pcie_write_cfg(priv, d, where, val); in imx_pcie_write_config()
A Dpcie_mediatek.c104 #define CFG_HEADER_DW1(where, size) \ argument
105 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
195 int where, int size, ulong *val) in mtk_pcie_hw_rd_cfg() argument
201 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_rd_cfg()
202 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_DEV(devfn), bus), in mtk_pcie_hw_rd_cfg()
218 *val = (*val >> (8 * (where & 3))) & 0xff; in mtk_pcie_hw_rd_cfg()
220 *val = (*val >> (8 * (where & 3))) & 0xffff; in mtk_pcie_hw_rd_cfg()
226 int where, int size, u32 val) in mtk_pcie_hw_wr_cfg() argument
231 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_wr_cfg()
232 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_DEV(devfn), bus), in mtk_pcie_hw_wr_cfg()
[all …]
A Dpcie_rockchip.c120 int where = rockchip_pcie_off_conf(bdf, offset); in rockchip_pcie_rd_conf() local
124 value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where); in rockchip_pcie_rd_conf()
130 value = readl(priv->axi_base + where); in rockchip_pcie_rd_conf()
147 int where = rockchip_pcie_off_conf(bdf, offset); in rockchip_pcie_wr_conf() local
151 old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where); in rockchip_pcie_wr_conf()
153 writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + where); in rockchip_pcie_wr_conf()
158 old = readl(priv->axi_base + where); in rockchip_pcie_wr_conf()
160 writel(value, priv->axi_base + where); in rockchip_pcie_wr_conf()
A Dpcie_iproc.c446 uint where, void **paddress) in iproc_pcie_map_ep_cfg_reg() argument
462 where & CFG_IND_ADDR_MASK); in iproc_pcie_map_ep_cfg_reg()
478 (where & CFG_ADDR_REG_NUM_MASK) | in iproc_pcie_map_ep_cfg_reg()
496 switch (where & ~0x3) { in iproc_pcie_fix_cap()
536 unsigned int devfn, int where, in iproc_pci_raw_config_read32() argument
542 ret = iproc_pcie_map_ep_cfg_reg(pcie->dev, devfn, where & ~0x3, &addr); in iproc_pci_raw_config_read32()
551 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in iproc_pci_raw_config_read32()
557 unsigned int devfn, int where, in iproc_pci_raw_config_write32() argument
564 ret = iproc_pcie_map_ep_cfg_reg(pcie->dev, devfn, where & ~0x3, &addr); in iproc_pci_raw_config_write32()
573 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); in iproc_pci_raw_config_write32()
[all …]
/u-boot/include/
A Dpci.h682 pci_dev_t, int where, u8 *), in pci_set_ops() argument
684 pci_dev_t, int where, u16 *), in pci_set_ops()
686 pci_dev_t, int where, u32 *), in pci_set_ops()
688 pci_dev_t, int where, u8), in pci_set_ops()
690 pci_dev_t, int where, u16), in pci_set_ops()
692 pci_dev_t, int where, u32)) { in pci_set_ops()
743 pci_dev_t dev, int where, u8 *val);
745 pci_dev_t dev, int where, u16 *val);
749 pci_dev_t dev, int where, u8 val);
790 pci_dev_t dev, int where, u8 val);
[all …]
/u-boot/arch/x86/cpu/baytrail/
A Dearly_uart.c52 static void x86_pci_write_config32(int dev, unsigned int where, u32 value) in x86_pci_write_config32() argument
56 addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3); in x86_pci_write_config32()
/u-boot/arch/x86/cpu/braswell/
A Dearly_uart.c47 static void x86_pci_write_config32(int dev, unsigned int where, u32 value) in x86_pci_write_config32() argument
51 addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3); in x86_pci_write_config32()
/u-boot/fs/squashfs/
A DKconfig9 filesystem use, for archival use (i.e. in cases where a .tar.gz file
11 embedded systems) where low overhead is needed.
/u-boot/drivers/video/bridge/
A DKconfig6 another. For example, where the SoC only supports eDP and the LCD
17 LVDS capability, or where LVDS requires too many signals to route
27 or where LVDS requires too many signals to route on the PCB.
/u-boot/board/friendlyarm/
A DKconfig23 determines (together with env. var. bootpart) where the OS (linux) is
30 (together with env. var. rootdev) where the OS (linux) is booted from.
/u-boot/board/freescale/mpc8313erdb/
A DREADME16 (where the '*' indicates the position of the tab of the switch.)
26 (where the '*' indicates the position of the tab of the switch.)
64 (where XXX is:
92 ...where 0x80000 is the filesize rounded up to
/u-boot/arch/x86/include/asm/acpi/cros_ec/
A Dals.asl35 * Returns a package of packages where each tuple consists of a pair
42 * Display luminance adjustment values are relative percentages where
/u-boot/board/freescale/mpc8315erdb/
A DREADME16 (where the '*' indicates the position of the tab of the switch.)
26 (where the '*' indicates the position of the tab of the switch.)
86 ...where 0x80000 is the filesize rounded up to
/u-boot/doc/device-tree-bindings/sysinfo/
A Dsysinfo.txt9 - compatible: any suitable string where the driver is in the UCLASS_SYSINFO
/u-boot/board/keymile/
A DKconfig49 Address where to load Linux kernel in RAM.
55 Address where to load flattened device tree in RAM.
96 Identifier number of I2C bus, where the inventory EEPROM is connected to.
/u-boot/arch/mips/include/asm/
A Dsystem.h256 extern void __die(const char *, struct pt_regs *, const char *where,
258 extern void __die_if_kernel(const char *, struct pt_regs *, const char *where,
/u-boot/board/aristainetos/
A Daxi.cfg10 * where:
A Dclocks2.cfg10 * where:
/u-boot/scripts/
A Dcleanpatch250 if ( !defined($where = tell(FILE)) ||
251 !truncate(FILE, $where) ) {
/u-boot/doc/
A DREADME.update11 updates. Each update in the update file has an address in NOR Flash where it
50 1.2.0 or later, must also be available on the system where the update file is
65 'update_uboot.its' file is where the U-Boot is stored in Flash, the
83 where the update will be placed is correct. Making mistake here and
A DREADME.falcon26 loading the kernel, passing to Linux the address in memory where
40 The address where to save it must be configured into board configuration
62 CONFIG_SYS_SPL_ARGS_ADDR Address in RAM where the parameters must be
66 CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND where the kernel is stored
68 CONFIG_CMD_SPL_NAND_OFS Offset in NAND where the parameters area was saved.
70 CONFIG_CMD_SPL_NOR_OFS Offset in NOR where the parameters area was saved.
111 This is the address where a kernel image is stored.
/u-boot/drivers/i2c/muxes/
A DKconfig25 response mechanism where masters have to claim the bus by asserting
35 I2C controller where driver handles proper routing to target i2c

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