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/u-boot/arch/arm/mach-rockchip/
A Dmake_fit_atf.py63 file.write('\t\t};\n')
64 file.write('\n')
78 file.write('\t\t};\n')
79 file.write('\n')
92 file.write('\n')
101 file.write(',')
109 file.write(';\n')
111 file.write('\t\t};\n')
112 file.write('\n')
123 file.write('\t};\n')
[all …]
/u-boot/test/dm/
A Dmmc.c33 char write[1024], read[1024]; in dm_test_mmc_blk() local
40 for (i = 0; i < sizeof(write); i++) in dm_test_mmc_blk()
41 write[i] = i; in dm_test_mmc_blk()
42 ut_asserteq(2, blk_dwrite(dev_desc, 0, 2, write)); in dm_test_mmc_blk()
44 ut_asserteq_mem(write, read, sizeof(write)); in dm_test_mmc_blk()
47 memset(write, '\0', sizeof(write)); in dm_test_mmc_blk()
50 ut_asserteq_mem(write, read, sizeof(write)); in dm_test_mmc_blk()
/u-boot/test/py/
A Dmultiplexed_log.py234 self.f.write('''\
313 self.f.write('''\
358 self.f.write('</pre>\n')
361 self.f.write('</div>\n')
362 self.f.write('</div>\n')
380 self.f.write('<pre>')
385 self.f.write('</a>')
387 self.f.write('</div>\n')
441 self.f.write('</div>\n')
442 self.f.write('</div>\n')
[all …]
/u-boot/board/synopsys/hsdk/
A Dheaderize-hsdk.py86 file.write(arc_id.to_bytes(2, byteorder='little'))
87 file.write(uboot_img_size.to_bytes(4, byteorder='little'))
88 file.write(check_sum.to_bytes(1, byteorder='little'))
89 file.write(image_copy_adr.to_bytes(4, byteorder='little'))
90 file.write(magic1.to_bytes(5, byteorder='big'))
91 file.write(jump_address.to_bytes(4, byteorder='little'))
95 file.write(0xFF.to_bytes(1, byteorder='little'))
96 file.write(flash_address.to_bytes(4, byteorder='little'))
98 file.write(flash_type.to_bytes(1, byteorder='little'))
103 fo.write(fi.read())
[all …]
/u-boot/drivers/net/phy/
A Dmscc.c299 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
302 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, in vsc8584_cmd()
313 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
329 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
341 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, in vsc8584_micro_deassert_reset()
353 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
368 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
388 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, in vsc8584_micro_assert_reset()
396 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
609 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, in vsc8584_patch_fw()
[all …]
/u-boot/board/synopsys/axs10x/
A Dheaderize-axs.py106 file.write(arc_id.to_bytes(2, byteorder='little'))
107 file.write(uboot_img_size.to_bytes(4, byteorder='little'))
108 file.write(check_sum.to_bytes(1, byteorder='little'))
109 file.write(image_copy_adr.to_bytes(4, byteorder='little'))
110 file.write(magic1.to_bytes(5, byteorder='big'))
111 for i in range(16): file.write(0x00.to_bytes(1, byteorder='little'))
112 for byte in magic2: file.write(byte.to_bytes(36, byteorder='big'))
114 file.write(0x00.to_bytes(1, byteorder='little'))
116 file.write(jump_address.to_bytes(4, byteorder='little'))
121 fo.write(fi.read())
[all …]
/u-boot/doc/
A DREADME.sata5 * Read/write raw blocks from/to SATA hard disk
17 1.1 How to raw write the kernel, file system, dtb to a SATA hard disk?
22 write kernel
24 => sata write 40000 0 2000
26 write ramdisk
28 => sata write 40000 2000 8000
30 write dtb
32 => sata write 40000 a000 1000
A DREADME.davinci.nand_spl8 we need a command, which switches between this two read/write
9 functions, so we can write the UBL header and the spl
16 between the two NAND read/write modes.
63 * we write before the real spl code
80 !! Don;t forget to switch to rbl nand read/write functions with
94 !! Don;t forget to switch to rbl nand read/write functions with
100 !! Don;t forget to switch to rbl nand read/write functions with
123 writeheader nandrbl rbl;nand erase 80000 ${pagesz};nand write 80000000 80000 ${pagesz};nandrbl uboot
124 writenand_spl nandrbl rbl;nand erase a0000 3000;nand write 80000800 a0000 3000;nandrbl uboot
125 writeuboot nandrbl uboot;nand erase c0000 5d000;nand write 80003800 c0000 5d000
[all …]
A DREADME.commands.spl23 nand write 0x80000100 0x680000 0x20000 /* write the image - one page */
31 nand write <adress shown by spl export> 0x680000 0x20000
/u-boot/drivers/spi/
A Dmxs_spi.c76 char *data, int length, int write, in mxs_spi_xfer_pio() argument
96 if (write) in mxs_spi_xfer_pio()
109 if (write) in mxs_spi_xfer_pio()
114 if (!write) { in mxs_spi_xfer_pio()
164 if (!write) in mxs_spi_xfer_dma()
173 if (write) in mxs_spi_xfer_dma()
192 if (write) in mxs_spi_xfer_dma()
250 if (!write) in mxs_spi_xfer_dma()
264 int write = 0; in mxs_spi_xfer() local
285 write = 1; in mxs_spi_xfer()
[all …]
/u-boot/board/sunxi/
A DREADME.nand7 read and write disturbs, data retention issues, bloks becoming
35 sunxi-fel write 0x4a000000 u-boot-dtb.bin
36 sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin
46 Then write the SPL and its backup:
48 nand write.raw.noverify 0x43000000 0 40
49 nand write.raw.noverify 0x43000000 0x400000 40
51 And finally write the U-Boot binary:
52 nand write 0x4a000000 0x800000 0xc0000
/u-boot/lib/zlib/
A Dinffast.c83 unsigned write; /* window write index */ in inflate_fast() local
118 write = state->write; in inflate_fast()
204 if (write == 0) { /* very common case */ in inflate_fast()
214 else if (write < op) { /* wrap around window */ in inflate_fast()
215 from += wsize + write - op; in inflate_fast()
216 op -= write; in inflate_fast()
223 if (write < len) { /* some from start of window */ in inflate_fast()
224 op = write; in inflate_fast()
234 from += write - op; in inflate_fast()
/u-boot/doc/imx/common/
A Dimx6.txt102 We can't use 'nand write' command to write SPL/firmware image directly
114 - followed by FCB setup, like first 2 blocks for FCB/DBBT write,
116 - write firmware at FW1 block and
117 - finally write fcb/dttb in first 2 block.
136 - write FW/SPL in FW1
137 - write FCB/DBBT in first 2 blocks
139 step-1: write SPL
147 NAND fw write: 0x80000 offset, 0xb000 bytes written: OK
149 step-2: write u-boot-dtb.img
160 icorem6qdl> nand write ${loadaddr} uboot ${filesize}
[all …]
/u-boot/drivers/pci/
A Dpci_compat.c28 PCI_HOSE_OP(write, byte, 8, u8)
29 PCI_HOSE_OP(write, word, 16, u16)
30 PCI_HOSE_OP(write, dword, 32, u32)
/u-boot/drivers/axi/
A Daxi_sandbox.c56 if (!ops || !ops->write) in axi_sandbox_write()
59 return ops->write(emul, address, data, size); in axi_sandbox_write()
69 .write = axi_sandbox_write,
A Daxi-uclass.c27 if (!ops->write) in axi_write()
30 return ops->write(dev, address, data, size); in axi_write()
/u-boot/drivers/misc/
A Dvexpress_config.c32 bool write, void *buf, int size) in vexpress_config_exec() argument
38 if (!write) { in vexpress_config_exec()
59 if (!write) in vexpress_config_exec()
89 .write = vexpress_config_write,
/u-boot/drivers/power/
A Dpower_spi.c19 static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write) in pmic_reg() argument
38 pmic_tx = p->hw.spi.prepare_tx(reg, val, write); in pmic_reg()
46 if (write) { in pmic_reg()
/u-boot/doc/usage/
A Dmbr.rst12 mbr write [interface] [device no] [partition list]
50 => mbr write mmc 0
69 The 'mbr write' command returns 0 on success write or 1 on failure.
85 | 0 | mbr write was succesful |
87 | 1 | mbr write failed |
/u-boot/drivers/dfu/
A DKconfig40 This option enables using DFU to read and write to MMC based storage.
47 This option enables using DFU to read and write to NAND based
60 This option enables using DFU to read and write RAM on the target.
65 This option enables using DFU to read and write to SPI flash based
81 This option enables using DFU to read and write to on any MTD device.
86 This option enables using DFU to read and write to VIRTUAL device
/u-boot/drivers/spmi/
A Dspmi-uclass.c29 if (!ops || !ops->write) in spmi_reg_write()
32 return ops->write(dev, usid, pid, reg, value); in spmi_reg_write()
/u-boot/test/py/tests/
A Dtest_ut.py16 fh.write(data)
22 fh.write(data)
/u-boot/board/buffalo/lsxl/
A Dkwbimage-lschl.cfg132 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
183 # bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
207 # bit0: 1, enable DDR init upon this register write
A Dkwbimage-lsxhl.cfg132 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
183 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
207 # bit0: 1, enable DDR init upon this register write
/u-boot/drivers/mtd/spi/
A Dsf-uclass.c26 return log_ret(sf_get_ops(dev)->write(dev, offset, len, buf)); in spi_flash_write_dm()
89 if (ops->write) in spi_flash_post_bind()
90 ops->write += gd->reloc_off; in spi_flash_post_bind()

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