Searched refs:write_aux_reg (Results 1 – 5 of 5) sorted by relevance
| /u-boot/arch/arc/lib/ |
| A D | cache.c | 285 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_enable()
294 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_disable()
389 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_entire_op()
394 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); in __slc_entire_op()
417 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); in slc_upper_region_init()
450 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_rgn_op()
506 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, in arc_ioc_setup()
606 write_aux_reg(ARC_AUX_IC_IVIC, 1); in __ic_entire_invalidate()
682 write_aux_reg(aux_cmd, paddr); in __dcache_line_loop()
699 write_aux_reg(ARC_AUX_DC_CTRL, ctrl); in __before_dc_op()
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| /u-boot/drivers/timer/ |
| A D | arc_timer.c | 74 write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); in arc_timer_probe()
76 write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); in arc_timer_probe()
78 write_aux_reg(ARC_AUX_TIMER0_CNT, 0); in arc_timer_probe()
82 write_aux_reg(ARC_AUX_TIMER1_CTRL, NH_MODE); in arc_timer_probe()
84 write_aux_reg(ARC_AUX_TIMER1_LIMIT, 0xffffffff); in arc_timer_probe()
86 write_aux_reg(ARC_AUX_TIMER1_CNT, 0); in arc_timer_probe()
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| /u-boot/arch/arc/include/asm/ |
| A D | arcregs.h | 118 #define write_aux_reg(reg_immed, val) \ macro
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| /u-boot/board/synopsys/hsdk/ |
| A D | hsdk.c | 275 write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT); in init_slave_cpu_func()
280 write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT); in init_slave_cpu_func()
298 write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val); in init_cluster_nvlim()
301 write_aux_reg(AUX_AUX_CACHE_LIMIT, val); in init_cluster_nvlim()
326 write_aux_reg(ARC_AUX_CSM_ENABLE, 0); in init_cluster_csm()
336 write_aux_reg(ARC_AUX_CSM_ENABLE, 1); in init_cluster_csm()
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| /u-boot/board/synopsys/iot_devkit/ |
| A D | iot_devkit.c | 130 write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1); in mach_cpu_init()
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