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/u-boot/include/andestech/
A Dandes_pcu.h98 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) argument
100 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument
101 #define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) argument
107 #define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) argument
126 #define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) argument
127 #define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) argument
129 #define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) argument
132 #define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) argument
133 #define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) argument
134 #define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) argument
[all …]
/u-boot/include/synopsys/
A Ddwcddr21mctl.h47 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument
48 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) argument
49 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) argument
50 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument
51 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument
52 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument
58 #define DWCDDR21MCTL_CCR_IB(x) ((x) << 29) argument
59 #define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30) argument
60 #define DWCDDR21MCTL_CCR_IT(x) ((x) << 31) argument
65 #define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0) argument
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/u-boot/board/samsung/odroid/
A Dsetup.h11 #define SDIV(x) ((x) & 0x7) argument
19 #define MUX_APLL_SEL(x) ((x) & 0x1) argument
81 #define MUX_C2C_SEL(x) ((x) & 0x1) argument
91 #define C2C_SEL(x) (((x)) & 0x7) argument
109 #define ACP_RATIO(x) ((x) & 0x7) argument
117 #define DIV_ACP(x) ((x) & 0x1) argument
159 #define UART0_SEL(x) ((x) & 0xf) argument
173 #define DIV_UART0(x) ((x) & 0x1) argument
188 #define DIV_MMC0(x) ((x) & 1) argument
205 #define DIV_MMC2(x) ((x) & 0x1) argument
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/u-boot/arch/arm/include/asm/arch-rockchip/
A Dvop_rk3288.h133 #define V_AUTO_GATING_EN(x) (((x) & 1) << 23) argument
134 #define V_STANDBY_EN(x) (((x) & 1) << 22) argument
135 #define V_DMA_STOP(x) (((x) & 1) << 21) argument
136 #define V_MMU_EN(x) (((x) & 1) << 20) argument
144 #define V_EDPI_HALT_EN(x) (((x)&1)<<8) argument
148 #define V_DIRECT_PATH_EN(x) ((x) & 1) argument
340 #define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0) argument
364 #define V_VSYNC(x) (((x)&0x1fff)<<0) argument
365 #define V_VERPRD(x) (((x)&0x1fff)<<16) argument
369 #define V_VAEP(x) (((x)&0x1fff)<<0) argument
[all …]
/u-boot/arch/m68k/include/asm/
A Dm5329.h17 #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) argument
18 #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) argument
19 #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) argument
20 #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) argument
21 #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) argument
22 #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) argument
96 #define PACR0(x) SCM_PACRA_PACR0(x) argument
97 #define PACR1(x) SCM_PACRA_PACR1(x) argument
98 #define PACR2(x) SCM_PACRA_PACR2(x) argument
99 #define PACR8(x) SCM_PACRB_PACR8(x) argument
[all …]
A Dm5301x.h13 #define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) argument
14 #define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) argument
15 #define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) argument
16 #define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12) argument
17 #define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8) argument
18 #define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4) argument
26 #define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8) argument
37 #define SCM_PACRC_PACR23(x) ((x) & 0x0F) argument
45 #define SCM_PACRD_PACR31(x) ((x) & 0x0F) argument
53 #define SCM_PACRE_PACR39(x) ((x) & 0x0F) argument
[all …]
A Dm520x.h13 #define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) argument
14 #define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) argument
15 #define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) argument
31 #define SCM_PACRC_PACR23(x) ((x) & 0x0F) argument
39 #define SCM_PACRD_PACR31(x) ((x) & 0x0F) argument
56 #define SCM_BMT_BMT(x) ((x) & 0x07) argument
169 #define GPIO_PDR_BE(x) ((x) & 0x0F) argument
172 #define GPIO_PDR_QSPI(x) ((x) & 0x0F) argument
174 #define GPIO_PDR_UART(x) ((x) & 0xFF) argument
175 #define GPIO_PDR_FECH(x) ((x) & 0xFF) argument
[all …]
A Dm547x_8x.h19 #define XARB_CFG_PM(x) (((x)&0x00000003)<<5) argument
20 #define XARB_CFG_SP(x) (((x)&0x00000007)<<8) argument
46 #define XARB_SIGCAP_TT(x) ((x)&0x0000001F) argument
56 #define XARB_PRI_M0P(x) (((x)&0x00000007)<<0) argument
57 #define XARB_PRI_M2P(x) (((x)&0x00000007)<<8) argument
64 #define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0) argument
87 #define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0) argument
88 #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2) argument
308 #define GPT_PWM_WIDTH(x) (x & 0xffff) argument
311 #define GPT_STA_CAPTURE(x) (x & 0xffff) argument
[all …]
A Dm5441x.h191 #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) argument
309 #define CCM_FNACR_MCC(x) ((x)&0xFFFF) argument
326 #define GPIO_PAR_FBCTL_TA(x) ((x)&3) argument
351 #define GPIO_PAR_BE_BS0(x) ((x)&0x03) argument
806 #define GPIO_URXD_WOM_U0(x) ((x)&3) argument
819 #define GPIO_HCR1_PB2_0(x) ((x)&7) argument
827 #define GPIO_HCR0_PH7_3(x) ((x)&0x1F) argument
839 #define PLL_CR_REFDIV(x) (((x)&7)<<8) argument
841 #define PLL_CR_FBKDIV(x) ((x)&0x3F) argument
857 #define PLL_DR_OUTDIV1(x) ((x)&0x1F) argument
[all …]
A Dm5235.h18 #define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) argument
22 #define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) argument
31 #define SCM_CWCR_CWT(x) (((x)&0x07)<<3) argument
48 #define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) argument
56 #define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) argument
274 #define GPIO_PODR_BS(x) ((x)&0x0F) argument
282 #define GPIO_PODR_UARTH(x) ((x)&0x03) argument
284 #define GPIO_PODR_QSPI(x) ((x)&0x1F) argument
286 #define GPIO_PODR_ETPU(x) ((x)&0x07) argument
368 #define GPIO_PAR_BS(x) ((x)&0x0F) argument
[all …]
A Dm5445x.h270 #define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) argument
349 #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) argument
350 #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) argument
376 #define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) argument
592 #define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) argument
659 #define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) argument
666 #define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) argument
687 #define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) argument
694 #define GPIO_DSCR_USB_USB(x) (((x)&0x03)) argument
701 #define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) argument
[all …]
/u-boot/arch/arm/include/asm/
A Dopcodes.h42 #define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) argument
43 #define ___asm_opcode_identity16(x) ((x) & 0xFFFF) argument
76 #define ___opcode_swab32(x) ___asm_opcode_swab32(x) argument
88 #define ___opcode_swab32(x) swab32(x) argument
89 #define ___opcode_swab16(x) swab16(x) argument
90 #define ___opcode_swahb32(x) swahb32(x) argument
91 #define ___opcode_swahw32(x) swahw32(x) argument
92 #define ___opcode_identity32(x) ((u32)(x)) argument
93 #define ___opcode_identity16(x) ((u16)(x)) argument
218 #define ___inst_arm(x) .long x argument
[all …]
/u-boot/include/faraday/
A Dftsdmc021.h48 #define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) argument
55 #define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) argument
57 #define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) argument
69 #define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1) argument
89 #define FTSDMC021_BANK_BASE(x) ((x) & 0xfff) argument
94 #define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0) argument
95 #define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4) argument
96 #define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8) argument
97 #define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12) argument
98 #define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16) argument
[all …]
/u-boot/arch/m68k/include/asm/coldfire/
A Dlcd.h50 #define LCDC_SSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) argument
54 #define LCDC_SR_YMAX(x) ((x)&0x000003FF) argument
57 #define LCDC_VPWR_VPW(x) (((x)&0x000003FF) argument
60 #define LCDC_CPR_CC(x) (((x)&0x00000003)<<30) argument
67 #define LCDC_CPR_CYP(x) ((x)&0x000003FF) argument
73 #define LCDC_CWHBR_BD(x) ((x)&0x000000FF) argument
113 #define LCDC_PCR_PCD(x) ((x)&0x0000003F) argument
140 #define LCDC_PCCR_PW(x) ((x)&0x000000FF) argument
145 #define LCDC_DCR_TM(x) ((x)&0x0000001F) argument
170 #define LCDC_GWSR_GWH(x) ((x)&0x000003FF) argument
[all …]
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) argument
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) argument
33 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) argument
45 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
65 #define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x)) argument
72 #define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x)) argument
74 #define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x)) argument
100 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
117 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) argument
143 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
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/u-boot/arch/arm/include/asm/arch-omap3/
A Domap3-regs.h23 #define CLKACTIVATIONTIME(x) (((x) & 3) << 25) argument
40 #define CSWROFFTIME(x) (((x) & 0x1f) << 16) argument
41 #define CSRDOFFTIME(x) (((x) & 0x1f) << 8) argument
43 #define CSONTIME(x) (((x) & 0xf) << 0) argument
46 #define ADVWROFFTIME(x) (((x) & 0x1f) << 16) argument
47 #define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) argument
49 #define ADVONTIME(x) (((x) & 0xf) << 0) argument
52 #define WEOFFTIME(x) (((x) & 0x1f) << 24) argument
54 #define WEONTIME(x) (((x) & 0xf) << 16) argument
55 #define OEOFFTIME(x) (((x) & 0x1f) << 8) argument
[all …]
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) argument
38 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
41 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
61 #define ICPU_DST_INTR_MAP(x) (0x94 + 0x4 * (x)) argument
66 #define ICPU_TIMER_VALUE(x) (0xe4 + 0x4 * (x)) argument
69 #define ICPU_TIMER_CTRL(x) (0xfc + 0x4 * (x)) argument
98 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
115 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) argument
146 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
166 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) argument
[all …]
/u-boot/include/
A Dcompiler.h95 # define cpu_to_le16(x) (x) argument
96 # define cpu_to_le32(x) (x) argument
97 # define cpu_to_le64(x) (x) argument
98 # define le16_to_cpu(x) (x) argument
99 # define le32_to_cpu(x) (x) argument
100 # define le64_to_cpu(x) (x) argument
114 # define cpu_to_be16(x) (x) argument
115 # define cpu_to_be32(x) (x) argument
116 # define cpu_to_be64(x) (x) argument
117 # define be16_to_cpu(x) (x) argument
[all …]
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2_icpu_cfg.h11 #define ICPU_GPR(x) (0x4 * (x)) argument
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 6) & GENMASK(7, 6)) argument
33 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4) argument
34 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4)) argument
49 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
69 #define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x)) argument
74 #define ICPU_TIMER_VALUE(x) (0x10c + 0x4 * (x)) argument
77 #define ICPU_TIMER_CTRL(x) (0x124 + 0x4 * (x)) argument
106 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
154 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
[all …]
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) argument
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) argument
33 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) argument
46 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
66 #define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x)) argument
71 #define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x)) argument
74 #define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x)) argument
103 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
120 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) argument
151 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
[all …]
/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) argument
36 #define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
42 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
44 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
45 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
89 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
106 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) argument
132 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
152 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) argument
183 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) argument
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/u-boot/drivers/ddr/altera/
A Dsdram_soc64.h83 (((x) >> 0) & 0x1F)
85 (((x) >> 5) & 0x1F)
87 (((x) >> 10) & 0xF)
89 (((x) >> 14) & 0x3)
91 (((x) >> 16) & 0x7)
94 (((x) >> 0) & 0xF)
96 (((x) >> 4) & 0x7)
98 (((x) >> 7) & 0x3)
100 (((x) >> 9) & 0x1F)
105 (((x) >> 5) & 0x3)
[all …]
/u-boot/drivers/ddr/microchip/
A Dddr2_regs.h46 #define REFCNT_CLK(x) (x) argument
47 #define REFDLY_CLK(x) ((x) << 16) argument
53 #define PWR_DN_DLY(x) ((x) << 4) argument
57 #define ECC_EN(x) (x) argument
63 #define ODTWLEN(x) ((x) << 20) argument
64 #define ODTRLEN(x) ((x) << 16) argument
65 #define ODTWDLY(x) ((x) << 12) argument
66 #define ODTRDLY(x) ((x) << 8) argument
70 #define MAX_BURST(x) ((x) << 24) argument
71 #define RDATENDLY(x) ((x) << 16) argument
[all …]
/u-boot/include/linux/byteorder/
A Dswab.h46 # define __arch__swab16(x) ___swab16(x) argument
49 # define __arch__swab32(x) ___swab32(x) argument
52 # define __arch__swab64(x) ___swab64(x) argument
56 # define __arch__swab16p(x) __swab16(*(x)) argument
59 # define __arch__swab32p(x) __swab32(*(x)) argument
66 # define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0) argument
69 # define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0) argument
72 # define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0) argument
93 # define __swab16(x) __fswab16(x) argument
94 # define __swab32(x) __fswab32(x) argument
[all …]
/u-boot/examples/standalone/
A Dstubs.c7 #define FO(x) offsetof(struct jt_funcs, x) argument
23 #x ":\n" \
36 #x ":\n" \
51 #x ":\n" \
64 #x ":\n" \
81 #x ":\n" \
97 #x ":\n" \
110 #x ":\n" \
126 #x ":\n" \
172 #x ":\n" \
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