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/u-boot/arch/arm/cpu/armv8/
A Dstart.S64 ands x0, x0, #0xfff
98 add x0, x0, x9
154 orr x0, x0, #0x40
207 and x0, x0, x1
250 and x0, x0, #0xf
256 orr x0, x0, #1 << 44
267 orr x0, x0, #1 << 49
269 orr x0, x0, #3 << 25
271 orr x0, x0, #3 << 27
300 orr x0, x0, #1 << 4
[all …]
/u-boot/arch/arm/mach-imx/imx8m/
A Dlowlevel_init.S20 adr x0, rom_pointer
21 stp x1, x2, [x0], #16
22 stp x3, x4, [x0], #16
23 stp x5, x6, [x0], #16
24 stp x7, x8, [x0], #16
37 str x30, [x0], #8
44 adr x0, rom_pointer
60 ldr x0, [x0]
61 mov sp, x0
66 cmp x0, #0
[all …]
/u-boot/arch/arm/lib/
A Dcrt0_64.S78 add x0, x0, #:lo12:__bss_start
82 add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
87 mov x0, sp
89 mov sp, x0
94 mov x0, #0
111 add x0, x0, #:lo12:_start
133 cmp x0, #0
141 cmp x0, #0
142 csel x0, x0, x1, ne
143 mov sp, x0
[all …]
A Dsetjmp_aarch64.S13 stp x19, x20, [x0,#0]
14 stp x21, x22, [x0,#16]
15 stp x23, x24, [x0,#32]
16 stp x25, x26, [x0,#48]
17 stp x27, x28, [x0,#64]
20 str x2, [x0, #96]
21 mov x0, #0
28 ldp x19, x20, [x0,#0]
34 ldr x2, [x0,#96]
37 adds x0, xzr, x1
[all …]
/u-boot/arch/arm/mach-mvebu/armada8k/
A Dcache_llc.S17 mov x0, #LLC_BASE_ADDR
18 add x0, x0, #LLC_FLUSH_BY_WAY
19 movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
21 str w1, [x0]
23 mov x0, #LLC_BASE_ADDR
24 add x0, x0, #LLC_CACHE_SYNC
26 str wzr, [x0]
28 mov x0, #LLC_BASE_ADDR
29 add x0, x0, #LLC_CACHE_SYNC_COMPLETE
31 1: ldr w1, [x0]
[all …]
/u-boot/arch/x86/include/asm/acpi/
A Dsleepstates.asl9 Name(\_S0, Package(){0x0,0x0,0x0,0x0})
11 Name(\_S1, Package(){0x1,0x0,0x0,0x0})
13 Name(\_S3, Package(){0x5,0x0,0x0,0x0})
15 Name(\_S4, Package(){0x6,0x0,0x0,0x0})
16 Name(\_S5, Package(){0x7,0x0,0x0,0x0})
/u-boot/arch/arm/dts/
A Dfsl-ls1046a.dtsi42 reg = <0x0 0x1ee1000 0x0 0x1000>;
51 reg = <0x0 0x2100000 0x0 0x10000>;
64 reg = <0x0 0x2110000 0x0 0x10000>;
75 reg = <0x0 0x1560000 0x0 0x10000>;
83 reg = <0x0 0x2300000 0x0 0x10000>;
93 reg = <0x0 0x2310000 0x0 0x10000>;
103 reg = <0x0 0x2320000 0x0 0x10000>;
113 reg = <0x0 0x2330000 0x0 0x10000>;
123 reg = <0x0 0x1530000 0x0 0x10000>;
187 reg = <0x0 0x21d0500 0x0 0x100>;
[all …]
A Dfsl-ls1043a.dtsi43 reg = <0x0 0x1ee1000 0x0 0x1000>;
52 reg = <0x0 0x2100000 0x0 0x10000>;
65 reg = <0x0 0x2110000 0x0 0x10000>;
76 reg = <0x0 0x1560000 0x0 0x10000>;
84 reg = <0x0 0x2300000 0x0 0x10000>;
94 reg = <0x0 0x2310000 0x0 0x10000>;
104 reg = <0x0 0x2320000 0x0 0x10000>;
114 reg = <0x0 0x2330000 0x0 0x10000>;
124 reg = <0x0 0x1530000 0x0 0x10000>;
188 reg = <0x0 0x21d0500 0x0 0x100>;
[all …]
A Dbcm68360.dtsi25 reg = <0x0 0x0>;
81 reg = <0x0 0xff800480 0x0 0x14>;
87 reg = <0x0 0xff8004c0 0x0 0x14>;
98 reg = <0x0 0xff800640 0x0 0x18>;
106 reg = <0x0 0xff800800 0x0 0xe4>;
113 reg = <0x0 0xff800500 0x0 0x4>,
114 <0x0 0xff800520 0x0 0x4>;
123 reg = <0x0 0xff800504 0x0 0x4>,
124 <0x0 0xff800524 0x0 0x4>;
133 reg = <0x0 0xff800508 0x0 0x4>,
[all …]
A Dbcm63158.dtsi25 reg = <0x0 0x0>;
105 reg = <0x0 0xff800800 0x0 0xe4>;
112 reg = <0x0 0xff800480 0x0 0x14>;
118 reg = <0x0 0xff8004c0 0x0 0x14>;
129 reg = <0x0 0xff800500 0x0 0x4>,
130 <0x0 0xff800520 0x0 0x4>;
139 reg = <0x0 0xff800504 0x0 0x4>,
140 <0x0 0xff800524 0x0 0x4>;
149 reg = <0x0 0xff800508 0x0 0x4>,
150 <0x0 0xff800528 0x0 0x4>;
[all …]
A Dbcm6858.dtsi25 reg = <0x0 0x0>;
97 reg = <0x0 0xff800640 0x0 0x18>;
105 reg = <0x0 0xff800800 0x0 0xe4>;
112 reg = <0x0 0xff802780 0x0 0x14>;
118 reg = <0x0 0xff8027c0 0x0 0x14>;
129 reg = <0x0 0xff800500 0x0 0x4>,
130 <0x0 0xff800520 0x0 0x4>;
139 reg = <0x0 0xff800504 0x0 0x4>,
140 <0x0 0xff800524 0x0 0x4>;
149 reg = <0x0 0xff800508 0x0 0x4>,
[all …]
A Dmeson-gx.dtsi30 reg = <0x0 0x0 0x0 0x1000000>;
36 reg = <0x0 0x10000000 0x0 0x200000>;
84 reg = <0x0 0x0>;
265 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
436 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
440 reg = <0x0 0x0 0x0 0x100>;
519 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
523 reg = <0x0 0x0 0x0 0x4>;
532 ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
545 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
[all …]
A Dfsl-lx2160a.dtsi48 reg = <0x0 0x80000000 0x0 0x200000>;
64 reg = <0x0 0x20c0000 0x0 0x10000>,
65 <0x0 0x20000000 0x0 0x10000000>;
77 reg = <0x0 0x2000000 0x0 0x10000>;
87 reg = <0x0 0x2010000 0x0 0x10000>;
96 reg = <0x0 0x2020000 0x0 0x10000>;
105 reg = <0x0 0x2030000 0x0 0x10000>;
114 reg = <0x0 0x2040000 0x0 0x10000>;
149 reg = <0x0 0x21c0000 0x0 0x1000>;
156 reg = <0x0 0x21d0000 0x0 0x1000>;
[all …]
A Dfsl-ls1088a.dtsi32 reg = <0x0 0x80000000 0x0 0x100000>;
48 reg = <0x0 0x2000000 0x0 0x10000>;
56 reg = <0x0 0x2010000 0x0 0x10000>;
64 reg = <0x0 0x2020000 0x0 0x10000>;
72 reg = <0x0 0x2030000 0x0 0x10000>;
79 reg = <0x0 0x21c0500 0x0 0x100>;
87 reg = <0x0 0x21c0600 0x0 0x100>;
96 reg = <0x0 0x2100000 0x0 0x10000>;
105 reg = <0x0 0x20c0000 0x0 0x10000>,
106 <0x0 0x20000000 0x0 0x10000000>;
[all …]
A Dfsl-ls1012a.dtsi39 reg = <0x0 0x1ee1000 0x0 0x1000>;
48 reg = <0x0 0x2100000 0x0 0x10000>;
59 reg = <0x0 0x1560000 0x0 0x10000>;
67 reg = <0x0 0x1580000 0x0 0x10000>;
76 reg = <0x0 0x2300000 0x0 0x10000>;
86 reg = <0x0 0x2310000 0x0 0x10000>;
98 reg = <0x0 0x2180000 0x0 0x10000>;
109 reg = <0x0 0x2190000 0x0 0x10000>;
134 reg = <0x0 0x1550000 0x0 0x10000>,
135 <0x0 0x40000000 0x0 0x4000000>;
[all …]
A Dfsl-ls2080a.dtsi32 reg = <0x0 0x80000000 0x0 0x100000>;
47 reg = <0x0 0x21c0500 0x0 0x100>;
55 reg = <0x0 0x21c0600 0x0 0x100>;
65 reg = <0x0 0x2000000 0x0 0x10000>;
74 reg = <0x0 0x2010000 0x0 0x10000>;
83 reg = <0x0 0x2020000 0x0 0x10000>;
92 reg = <0x0 0x2030000 0x0 0x10000>;
100 reg = <0x0 0x2100000 0x0 0x10000>;
109 reg = <0x0 0x20c0000 0x0 0x10000>,
110 <0x0 0x20000000 0x0 0x10000000>;
[all …]
A Dfsl-ls1028a.dtsi26 reg = <0x0 0x1300000 0x0 0xa0000>;
49 reg = <0x0 0x80000000 0x0 0x100000>;
69 reg = <0x0 0x20c0000 0x0 0x10000>,
70 <0x0 0x20000000 0x0 0x10000000>;
81 reg = <0x0 0x21c0500 0x0 0x100>;
89 reg = <0x0 0x21c0600 0x0 0x100>;
129 bus-range = <0x0 0x0>;
219 reg = <0x0 0x2000000 0x0 0x10000>;
305 reg = <0x0 0x2260000 0x0 0x1000>;
315 reg = <0x0 0x2270000 0x0 0x1000>;
[all …]
A Dmeson-g12-common-u-boot.dtsi18 reg = <0x0 0xff900000 0x0 0x100000>,
19 <0x0 0xff63c000 0x0 0x1000>,
20 <0x0 0xff638000 0x0 0x400>;
26 reg = <0x0 0x0 0x0 0x10000>,
27 <0x0 0x3c000 0x0 0x1000>;
A Dphytium-durian.dts20 reg = <0x0 0x40000000 0x0 0x10000000>;
21 bus-range = <0x0 0xff>;
22 ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xF00000>,
23 <0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000>,
29 reg = <0x0 0x28001000 0x0 0x1000>;
/u-boot/arch/arm/cpu/armv8/bcmns3/
A Dlowlevel.S14 mov x1, x0
21 mov x0, #0x18
25 ldr x2, [x0]
34 add x0, x0, #0x10000 /* move to next node */
38 mov x0, x7
43 mov x1, x0
49 ldr x2, [x0]
53 add x0, x0, #0x10000 /* move to next node */
74 cbz x0, 1f
83 cbz x0, 1f
[all …]
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dlowlevel.S82 orr x0, x0, #0x20 /* AMO */
341 str x2, [x0]
342 add x0, x0, #8
343 cmp x0, x1
352 str w1, [x0]
354 str w1, [x0]
372 mov x1, x0
382 add x0, x0, #0x10000 /* move to next node */
389 mov x1, x0
399 add x0, x0, #0x10000 /* move to next node */
[all …]
/u-boot/arch/powerpc/dts/
A Dp2020rdb-pc.dts19 ranges = <0x0 0x0 0xffe00000 0x100000>;
23 reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
28 reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
29 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
30 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
34 reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
35 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
36 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
A Dp1020rdb-pc.dts19 ranges = <0x0 0x0 0xffe00000 0x100000>;
23 reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
24 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
25 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
29 reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
30 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
31 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
/u-boot/board/cortina/presidio-asic/
A Dlowlevel_init.S20 mrs x0, s3_1_c15_c2_1
21 tst x0, #0x40
23 orr x0, x0, #0x40
24 msr s3_1_c15_c2_1, x0
32 str w1, [x0]
36 branch_if_slave x0, 1f
38 ldr x0, =GICD_BASE
43 ldr x0, =GICR_BASE
46 ldr x0, =GICD_BASE
53 branch_if_master x0, x1, 2f
[all …]
/u-boot/arch/x86/dts/
A Dcrownbay.dts77 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
84 reg = <0x0000b800 0x0 0x0 0x0 0x0>;
91 reg = <0x00010000 0x0 0x0 0x0 0x0>;
100 reg = <0x00025100 0x0 0x0 0x0 0x0
101 0x01025110 0x0 0x0 0x0 0x0>;
114 reg = <0x00025200 0x0 0x0 0x0 0x0
115 0x01025210 0x0 0x0 0x0 0x0>;
128 reg = <0x00025300 0x0 0x0 0x0 0x0
129 0x01025310 0x0 0x0 0x0 0x0>;
142 reg = <0x00025400 0x0 0x0 0x0 0x0
[all …]

Completed in 29 milliseconds

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