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/u-boot/arch/arm/dts/
A Dzynq-zc770-xm011-x16.dts3 * Xilinx ZC770 XM011 board DTS with NAND x16
10 model = "Xilinx ZC770 XM011 board (NAND x16)";
A Dtegra20-harmony.dts570 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
571 MATRIX_KEY(0x16, 0x02, KEY_KP6)
572 MATRIX_KEY(0x16, 0x03, KEY_KP5)
573 MATRIX_KEY(0x16, 0x04, KEY_KP3)
574 MATRIX_KEY(0x16, 0x05, KEY_KP2)
575 MATRIX_KEY(0x16, 0x07, KEY_KP0)
A Dfsl-ls2080a.dtsi230 0x16 0x00000000 0x0 0x20000>; /* configuration space */
237 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
238 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
A Dimx8mq-evk.dts463 MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
470 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
611 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
A Dtegra20-seaboard.dts699 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
700 MATRIX_KEY(0x16, 0x02, KEY_KP6)
701 MATRIX_KEY(0x16, 0x03, KEY_KP5)
702 MATRIX_KEY(0x16, 0x04, KEY_KP3)
703 MATRIX_KEY(0x16, 0x05, KEY_KP2)
704 MATRIX_KEY(0x16, 0x07, KEY_KP0)
A Dsocfpga_arria10_socdk.dtsi146 reg = <0x16>;
A Darmada-38x-controlcenterdc.dts331 reg = <0x16>;
435 reg = <0x16>;
/u-boot/board/boundary/nitrogen6x/
A Dddr-setup.cfg19 * memory bus width: 64 bits x16/x32/x64
21 * memory bus width: 64 bits x16/x32/x64
23 * memory bus width: 32 bits x16/x32
/u-boot/arch/arm/mach-imx/imx8m/
A Dlowlevel_init.S28 stp x15, x16, [x0], #16
52 ldp x15, x16, [x0], #16
/u-boot/arch/arm/cpu/armv8/xen/
A Dhypercall.S59 mov x16, #__HYPERVISOR_##hypercall; \
/u-boot/arch/mips/mach-mscc/
A DKconfig71 bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
74 bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
/u-boot/arch/arm/cpu/armv8/
A Dexceptions.S55 stp x15, x16, [sp, #-16]!
128 ldp x15, x16, [sp],#16
/u-boot/arch/riscv/cpu/
A Dmtrap.S49 SREG x16, 16 * REGBYTES(sp)
86 LREG x16, 16 * REGBYTES(sp)
/u-boot/board/alliedtelesis/SBx81LIFKW/
A Dkwbimage.cfg21 # Dram initalization for 1 x x16
/u-boot/board/alliedtelesis/SBx81LIFXCAT/
A Dkwbimage.cfg21 # Dram initalization for 1 x x16
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dlowlevel.S259 mov x16, #0x10000
260 mul x14, \xreg, x16
/u-boot/board/LaCie/net2big_v2/
A Dkwbimage.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
60 # bit1-0: 01, Cs0width=x16
/u-boot/configs/
A Dxilinx_zynq_virt_defconfig55 CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-z…
/u-boot/lib/efi_loader/
A Defi_image_loader.c133 uint16_t *x16 = efi_reloc + offset; in efi_loader_relocate() local
139 *x16 += ((uint32_t)delta) >> 16; in efi_loader_relocate()
142 *x16 += (uint16_t)delta; in efi_loader_relocate()
/u-boot/doc/device-tree-bindings/fsp/fsp2/apollolake/
A Dfsp-m.txt94 0x16: DDR3_1600_8_8_8
146 1: x16
222 4: x16
/u-boot/arch/x86/dts/
A Dchromebook_samus.dts388 * columns 11, density 4096 mb, x16
428 * columns 11, density 8192 mb, x16
468 * columns 11, density 8192 mb, x16
/u-boot/doc/device-tree-bindings/sound/
A Dda7219.txt106 dlg,d-b-btn-thr = <0x16>;
/u-boot/board/Seagate/nas220/
A Dkwbimage.cfg26 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
/u-boot/doc/develop/
A Dcrash_dumps.rst35 x16: 000000007ff291fc x17: 0000000000000000
/u-boot/board/Marvell/sheevaplug/
A Dkwbimage.cfg21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz

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