| /u-boot/arch/arm/cpu/armv8/ |
| A D | fel_utils.S | 35 adr x2, fel_stash
36 str w0, [x2]
37 str w1, [x2, #4]
44 ldr x2, =(SUNXI_R_CPUCFG_BASE + 0x1c0)
45 str w0, [x2], #0x4
47 ldr x2, =(SUNXI_RTC_BASE + 0x1b8) // BOOT_CPU_HP_FLAG_REG
48 str w0, [x2], #0x4
50 ldr x2, =(SUNXI_CPUCFG_BASE + 0x1a4) // offset for CPU hotplug base
51 str w0, [x2, #0x8]
54 str w0, [x2]
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| A D | cache.S | 31 add x2, x2, #4 /* x2 <- log2(cache line size) */
48 lsl x7, x4, x2
136 mov x2, #4
137 lsl x2, x2, x3 /* cache line size */
140 sub x3, x2, #1
143 add x0, x0, x2
162 mov x2, #4
163 lsl x2, x2, x3 /* cache line size */
166 sub x3, x2, #1
169 add x0, x0, x2
[all …]
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| A D | exceptions.S | 62 stp x1, x2, [sp, #-16]!
79 mrs x2, elr_el3
82 mrs x2, elr_el2
85 mrs x2, elr_el1
87 stp x2, x0, [sp, #-16]!
101 ldp x2, x0, [sp],#16
103 3: msr elr_el3, x2
105 2: msr elr_el2, x2
107 1: msr elr_el1, x2
121 ldp x1, x2, [sp],#16
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| A D | sec_firmware_asm.S | 33 str w3, [x2]
47 mov x2, 0x0
68 mov x3, x2
69 mov x2, x1
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| A D | start.S | 88 adrp x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
89 add x2, x2, #:lo12:__rel_dyn_start
93 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
94 ldr x4, [x2], #8 /* x4 <- addend */
102 cmp x2, x3
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| /u-boot/arch/arm/lib/ |
| A D | relocate_64.S | 48 adrp x2, __image_copy_end /* x2 <- address bits [31:12] */
49 add x2, x2, :lo12:__image_copy_end /* x2 <- address bits [11:00] */
53 cmp x1, x2 /* until source end address [x2] */
60 adrp x2, __rel_dyn_start /* x2 <- address bits [31:12] */
61 add x2, x2, :lo12:__rel_dyn_start /* x2 <- address bits [11:00] */
65 ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
66 ldr x4, [x2], #8 /* x4 <- addend */
76 cmp x2, x3
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| A D | setjmp_aarch64.S | 19 mov x2, sp
20 str x2, [x0, #96]
34 ldr x2, [x0,#96]
35 mov sp, x2
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| A D | ccn504.S | 29 str x9, [x0, x2]
30 1: ldr x10, [x0, x2]
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| /u-boot/arch/arm/cpu/armv8/bcmns3/ |
| A D | lowlevel.S | 25 ldr x2, [x0]
26 cmp x2, x1 /* check status */
49 ldr x2, [x0]
50 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
51 orr x2, x2, x1
52 str x2, [x0]
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| /u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| A D | lowlevel.S | 39 ldr x2, =DCFG_CCSR_SVR
40 ldr w2, [x2]
49 ldr x2, =SCFG_GIC400_ALIGN
50 ldr w2, [x2]
339 mov x2, #0
341 str x2, [x0]
377 ldr x2, [x0]
395 ldr x2, [x0]
396 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
397 orr x2, x2, x1
[all …]
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| /u-boot/arch/arm/dts/ |
| A D | rk3288-evb.dts | 19 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
22 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
25 0x0 0xc3 0x6 0x2>;
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| A D | rk3288-rock-pi-n8-u-boot.dtsi | 15 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
18 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
21 0x0 0xc3 0x6 0x2>;
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| A D | rk3288-veyron-speedy-u-boot.dtsi | 9 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
12 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
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| A D | rk3288-tinker-u-boot.dtsi | 10 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
13 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
16 0x0 0xc3 0x6 0x2>;
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| A D | armada-7040-db-nand.dts | 116 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
117 0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
119 0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
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| A D | armada-380.dtsi | 55 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
56 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
87 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
88 0x81000000 0 0 0x81000000 0x2 0 1 0>;
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| A D | ste-dbx5x0.dtsi | 497 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
499 <&dma 37 0 0x2>, /* Logical - DevToMem */
501 <&dma 36 0 0x2>, /* Logical - DevToMem */
503 <&dma 19 0 0x2>, /* Logical - DevToMem */
505 <&dma 18 0 0x2>, /* Logical - DevToMem */
507 <&dma 17 0 0x2>, /* Logical - DevToMem */
509 <&dma 16 0 0x2>, /* Logical - DevToMem */
511 <&dma 39 0 0x2>, /* Logical - DevToMem */
749 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
765 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
[all …]
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| /u-boot/arch/arm/mach-mediatek/mt8512/ |
| A D | lowlevel_init.S | 23 mov x3, x2
24 mov x2, x1
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| /u-boot/arch/arm/mach-mediatek/mt8518/ |
| A D | lowlevel_init.S | 23 mov x3, x2
24 mov x2, x1
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| /u-boot/arch/arm/mach-imx/imx8m/ |
| A D | lowlevel_init.S | 21 stp x1, x2, [x0], #16
45 ldp x1, x2, [x0], #16
68 mov x3, x2
69 mov x2, x1
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| /u-boot/arch/arm/cpu/armv8/xen/ |
| A D | lowlevel_init.S | 22 stp x0, x2, [x1], #16
31 ldp x0, x2, [x1], #16
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| /u-boot/arch/arm/include/asm/arch-tegra/ |
| A D | cboot.h | 16 unsigned long x2, unsigned long x3);
23 unsigned long x2, unsigned long x3) in cboot_save_boot_params() argument
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| /u-boot/arch/x86/include/asm/arch-apollolake/acpi/ |
| A D | gpiolib.asl | 21 Method (SPC0, 0x2, Serialized)
46 Method (SPC1, 0x2, Serialized)
59 Method (GDW0, 0x2, Serialized)
80 Method (GHO, 0x2, Serialized)
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| /u-boot/arch/riscv/dts/ |
| A D | ae350_32.dts | 244 interrupt-parent = <0x2>;
251 interrupt-parent = <0x2>;
258 interrupt-parent = <0x2>;
265 interrupt-parent = <0x2>;
272 interrupt-parent = <0x2>;
279 interrupt-parent = <0x2>;
286 interrupt-parent = <0x2>;
293 interrupt-parent = <0x2>;
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| A D | ae350_64.dts | 244 interrupt-parent = <0x2>;
251 interrupt-parent = <0x2>;
258 interrupt-parent = <0x2>;
265 interrupt-parent = <0x2>;
272 interrupt-parent = <0x2>;
279 interrupt-parent = <0x2>;
286 interrupt-parent = <0x2>;
293 interrupt-parent = <0x2>;
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