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Searched refs:zero (Results 1 – 25 of 143) sorted by relevance

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/u-boot/board/imgtec/malta/
A Dlowlevel_init.S192 sw zero, MSC01_PCI_HEAD3_OFS(t0)
193 sw zero, MSC01_PCI_HEAD4_OFS(t0)
194 sw zero, MSC01_PCI_HEAD5_OFS(t0)
195 sw zero, MSC01_PCI_HEAD6_OFS(t0)
196 sw zero, MSC01_PCI_HEAD7_OFS(t0)
197 sw zero, MSC01_PCI_HEAD8_OFS(t0)
198 sw zero, MSC01_PCI_HEAD9_OFS(t0)
199 sw zero, MSC01_PCI_HEAD10_OFS(t0)
200 sw zero, MSC01_PCI_HEAD12_OFS(t0)
201 sw zero, MSC01_PCI_HEAD13_OFS(t0)
[all …]
/u-boot/arch/mips/cpu/
A Dstart.S30 MTC0 zero, CP0_WATCHLO,\sel
65 PTR_S zero, 0(t0)
131 mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
194 MTC0 zero, CP0_WATCHLO
195 mtc0 zero, CP0_WATCHHI
199 mtc0 zero, CP0_CAUSE
202 mtc0 zero, CP0_COMPARE
278 move a0, zero # a0 <-- boot_flags = 0
282 move ra, zero
/u-boot/arch/mips/lib/
A Dcache_init.S53 move \sz, zero
131 move R_L2_SIZE, zero
132 move R_L2_LINE, zero
133 move R_L2_BYPASSED, zero
134 move R_L2_L2C, zero
191 sw zero, GCR_L2_DATA(t0)
232 mtc0 zero, CP0_TAGLO, 4
271 f_fill64 a0, -64, zero
303 mtc0 zero, CP0_TAGLO
304 mtc0 zero, CP0_TAGLO, 2
[all …]
/u-boot/arch/riscv/cpu/
A Dstart.S58 mv gp, zero
72 csrw MODE_PREFIX(ie), zero
154 amoswap.w.rl zero, zero, 0(t0)
176 amoswap.w.rl zero, zero, 0(t0)
193 mv a0, zero /* a0 <-- boot_flags = 0 */
204 SREG zero, 0(t0)
230 mv a3, zero
245 mv a0, zero
246 mv a1, zero
357 SREG zero, 0(t0) /* clear loop... */
[all …]
/u-boot/board/synopsys/axs10x/
A Daxs10x.c32 void board_jump_and_run(ulong entry, int zero, int arch, uint params) in board_jump_and_run() argument
34 void (*kernel_entry)(int zero, int arch, uint params); in board_jump_and_run()
40 kernel_entry(zero, arch, params); in board_jump_and_run()
/u-boot/arch/arc/lib/
A Dbootm.c70 __weak void board_jump_and_run(ulong entry, int zero, int arch, uint params) in board_jump_and_run() argument
72 void (*kernel_entry)(int zero, int arch, uint params); in board_jump_and_run()
76 kernel_entry(zero, arch, params); in board_jump_and_run()
/u-boot/doc/device-tree-bindings/arm/
A Dl2c2x0.txt62 non-zero, disable if zero.
64 if non-zero, disable if zero.
66 if non-zero, disable if zero.
67 - arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
68 disable if zero.
94 - arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero
/u-boot/arch/mips/include/asm/
A Dregdef.h19 #define zero $0 /* wired zero */ macro
62 #define zero $0 /* wired zero */ macro
/u-boot/arch/mips/mach-octeon/
A Dlowlevel_init.S25 dins a0, zero, 0, 9
66 ins t2, zero, 0, 7 /* Round up to cache line for memcpy */
114 dins a0, zero, 0, 9
/u-boot/arch/mips/mach-mscc/
A Dlowlevel_init_luton.S26 bne v1, zero, 1f
46 beq v1, zero, 2b
/u-boot/arch/mips/mach-jz47xx/
A Dstart.S63 mtc0 zero, CP0_TAGLO
64 mtc0 zero, CP0_TAGHI
/u-boot/arch/mips/mach-pic32/
A Dlowlevel_init.S21 mtc0 zero, CP0_WIRED
/u-boot/configs/
A DLicheePi_Zero_defconfig6 CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
A Dbananapi_m2_zero_defconfig7 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-m2-zero"
A Dorangepi_zero_plus_defconfig8 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus"
A Dorangepi_zero_plus2_h3_defconfig9 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2"
/u-boot/board/Seagate/nas220/
A Dkwbimage.cfg29 # bit23-14: zero
32 # bit29-26: zero
61 # bit31-13: zero required
94 # bit12: 0, PD must be zero
140 # bit31-4: zero, required
/u-boot/arch/mips/mach-mtmips/mt7628/
A Dlowlevel_init.S69 ins t0, zero, 30, 2
77 mtc0 zero, CP0_TAGLO /* Zero to DDataLo */
88 mtc0 zero, CP0_TAGLO, 2
/u-boot/board/Marvell/sheevaplug/
A Dkwbimage.cfg24 # bit23-14: zero
27 # bit29-26: zero
57 # bit31-13: zero required
89 # bit12: 0, PD must be zero
137 # bit31-4: zero, required
/u-boot/board/Seagate/dockstar/
A Dkwbimage.cfg27 # bit23-14: zero
30 # bit29-26: zero
60 # bit31-13: zero required
92 # bit12: 0, PD must be zero
140 # bit31-4: zero, required
/u-boot/board/Seagate/goflexhome/
A Dkwbimage.cfg30 # bit23-14: zero
33 # bit29-26: zero
63 # bit31-13: zero required
95 # bit12: 0, PD must be zero
143 # bit31-4: zero, required
/u-boot/board/Synology/ds109/
A Dkwbimage.cfg28 # bit23-14: zero
31 # bit29-26: zero
61 # bit31-13: zero required
93 # bit12: 0, PD must be zero
143 # bit31-4: zero, required
/u-boot/board/Marvell/dreamplug/
A Dkwbimage.cfg25 # bit23-14: zero
28 # bit29-26: zero
58 # bit31-13: zero required
90 # bit12: 0, PD must be zero
138 # bit31-4: zero, required
/u-boot/board/Marvell/guruplug/
A Dkwbimage.cfg24 # bit23-14: zero
27 # bit29-26: zero
57 # bit31-13: zero required
89 # bit12: 0, PD must be zero
137 # bit31-4: zero, required
/u-boot/board/qemu-mips/
A Dlowlevel_init.S36 mtc0 zero, CP0_WIRED

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