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/xen/tools/xentrace/
A Dformats29 0x00028008 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) sched_ctl
117 0x00082010 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) NMI
118 0x00082011 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) SMI
123 0x00082015 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) MCE
128 0x00082018 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) CLTS
200 0x00802001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) cleanup_move_delayed [ irq = %(1)d, vector 0x%(2)x …
201 0x00802002 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) cleanup_move [ irq = %(1)d, vector 0x%(2)x on CPU%(…
202 0x00802003 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) bind_vector [ irq = %(1)d = vector 0x%(2)x, CPU mas…
203 0x00802004 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) clear_vector [ irq = %(1)d = vector 0x%(2)x, CPU ma…
204 0x00802005 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) move_vector [ irq = %(1)d had vector 0x%(2)x on CPU…
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/xen/tools/misc/
A Dxen-hvmcrash.c116 if (descriptor->typecode == HVM_SAVE_CODE(CPU)) { in main()
117 HVM_SAVE_TYPE(CPU) *cpu; in main()
120 cpu = (HVM_SAVE_TYPE(CPU) *)(buf + off); in main()
A Dxen-hvmctx.c135 HVM_SAVE_TYPE(CPU) c; in dump_cpu()
445 case HVM_SAVE_CODE(CPU): dump_cpu(); break; in main()
/xen/docs/misc/
A Dvtd-pi.txt8 CPU-side posted-interrupts: posted-interrupts support in CPU side
44 followed by an optional notification event issued to the CPU.
101 More information about APICv and CPU-side Posted-interrupt, please refer
110 an optional notification event issued to the CPU complex. The interrupt
119 (interrupt) to be issued to the CPU complex to inform CPU/software about pending
224 This existing global vector is a _special_ vector to CPU, CPU handle it in a
227 for more information about how CPU handles it.
280 by vCPU1 incorrectly (remember this is a special vector to CPU). The worst
299 1. Get the physical CPU.
320 2. For lowest-priority interrupts, new Intel CPU/Chipset/root-complex
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A Dcrashdb.txt50 watchdog, and every other CPU, so the state of the world shouldn't
/xen/docs/man/
A Dxentrace.8.pod14 CPU(uint) TSC(u64) EVENT(u32) D1 D2 D3 D4 D5 (all u32)
16 Where CPU is the processor number, TSC is the record's timestamp
17 (the value of the CPU cycle counter), EVENT is the event ID and
41 =item B<-c> [I<c>|I<CPU-LIST>|I<all>], B<--cpu-mask>=[I<c>|I<CPU-LIST>|I<all>]
46 constructed. If using the I<CPU-LIST> it expects decimal numbers, which
A Dxlcpupool.cfg.5.pod92 =item B<cpus="CPU-LIST">
95 cpus must be free, or creation will fail. C<CPU-LIST> may be specified
A Dxentrace_format.1.pod27 These correspond to the CPU number, event ID, timestamp counter and
A Dxl.1.pod.in350 The domain is currently running on a CPU.
392 less utilized than a high CPU workload. Consider yourself warned.
784 CPU count configured at boot for the domain.
794 Some guests may need to actually bring the newly added CPU online
1048 A domain with a weight of 512 will get twice as much CPU as a domain
1054 The cap optionally fixes the maximum amount of CPU a domain will be
1056 is expressed in percentage of one physical CPU: 100 is 1 physical CPU,
1314 List CPU pools on the host.
1338 nodes can be specified as single CPU/node IDs or as ranges.
1348 plus CPU 8, but keeping out CPUs 10,11,12, in (c).
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A Dxl.conf.5.pod214 concerning CPU affinity. One example is CPU pools. Users should always double
/xen/docs/admin-guide/
A Dmicrocode-loading.rst9 needed by the CPU vendors.
30 Where possible, microcode should be loaded at boot time. This allows the CPU
50 model name : Intel(R) Xeon(R) CPU E3-1240 v3 @ 3.40GHz
64 correct blob for a specific CPU.
66 Tools such as Dracut will identify the correct blob for the current CPU, which
74 where the exact CPU details aren't known ahead of booting (e.g. install
A Dintroduction.rst38 and knows how to drive various CPU internal devices such as IOMMUs, but
/xen/xen/arch/arm/
A DKconfig101 This config option will take CPU-specific actions to harden the
140 the kernel if an affected CPU is detected.
163 only patch the kernel if an affected CPU is detected.
185 the kernel if an affected CPU is detected.
204 the kernel if an affected CPU is detected.
225 the kernel if an affected CPU is detected.
/xen/xen/drivers/passthrough/
A DKconfig25 translation table format and is able to use CPU's P2M table as is.
/xen/tools/tests/mce-test/tools/
A DREADME19 -c, --cpu=CPU_ID target CPU, the default is CPU0
/xen/tools/libxc/
A Dxc_pagetab.c45 HVM_SAVE_CODE(CPU), vcpu, in xc_translate_foreign_address()
/xen/docs/features/
A Dsched_rtds.pandoc15 RTDS is one of the virtual CPU (vCPU) scheduler available in the Xen
93 * run a CPU-burning process inside the VM (e.g., `yes`),
A Dfeature-levelling.pandoc32 * The CPU itself
187 The CPU feature flags are the only information which the toolstack has a
A Dsched_credit.pandoc15 Credit (also known as Credit1) is the old virtual CPU (vCPU) scheduler
/xen/tools/xenstat/xentop/
A DTODO6 * Make CPU in % more accurate
/xen/
A Dconfig.guess1007 CPU=mipsisa64r6
1010 CPU=mipsisa32r6
1013 CPU=mips64
1015 CPU=mips
1031 test "x$CPU" != x && { echo "$CPU${MIPS_ENDIAN}-unknown-linux-$LIBCABI"; exit; }
/xen/xen/drivers/char/
A DKconfig53 Instruments based CPU, say Y.
/xen/docs/
A Dglossary.rst42 the CPU architecture, and contrasted against hypervisor context/state.
/xen/docs/misc/arm/
A Dsilicon-errata.txt31 and patched in at runtime when an affected CPU is detected. Note that
/xen/tools/debugger/kdd/
A Dkdd-xen.c152 if (desc->typecode == HVM_SAVE_CODE(CPU)) { in kdd_count_cpus()
173 if (desc->typecode == HVM_SAVE_CODE(CPU) && desc->instance == cpuid) { in get_cpu()

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