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Searched refs:GICD_ICFGR (Results 1 – 6 of 6) sorted by relevance

/xen/xen/arch/arm/
A Dvgic-v2.c292 case VRANGE32(GICD_ICFGR, GICD_ICFGRN): in vgic_v2_distr_mmio_read()
297 rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD); in vgic_v2_distr_mmio_read()
300 icfgr = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)]; in vgic_v2_distr_mmio_read()
547 case VREG32(GICD_ICFGR): /* SGIs */ in vgic_v2_distr_mmio_write()
556 rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD); in vgic_v2_distr_mmio_write()
559 vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, in vgic_v2_distr_mmio_write()
A Dvgic-v3.c739 case VRANGE32(GICD_ICFGR, GICD_ICFGRN): in __vgic_v3_distr_common_mmio_read()
744 rank = vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD); in __vgic_v3_distr_common_mmio_read()
747 icfgr = rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WORD)]; in __vgic_v3_distr_common_mmio_read()
853 case VREG32(GICD_ICFGR): /* Restricted to configure SGIs */ in __vgic_v3_distr_common_mmio_write()
856 case VRANGE32(GICD_ICFGR + 4, GICD_ICFGRN): /* PPI + SPIs */ in __vgic_v3_distr_common_mmio_write()
860 rank = vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD); in __vgic_v3_distr_common_mmio_write()
863 vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, in __vgic_v3_distr_common_mmio_write()
1199 case VRANGE32(GICD_ICFGR, GICD_ICFGRN): in vgic_v3_distr_mmio_read()
1386 case VRANGE32(GICD_ICFGR, GICD_ICFGRN): in vgic_v3_distr_mmio_write()
A Dgic-v2.c301 cfg = readl_gicd(GICD_ICFGR + (irq / 16) * 4); in gicv2_set_irq_type()
307 writel_gicd(cfg, GICD_ICFGR + (irq / 16) * 4); in gicv2_set_irq_type()
309 actual = readl_gicd(GICD_ICFGR + (irq / 16) * 4); in gicv2_set_irq_type()
368 writel_gicd(0x0, GICD_ICFGR + (i / 16) * 4); in gicv2_dist_init()
A Dgic-v3.c547 base = GICD + GICD_ICFGR + (irq / 16) * 4; in gicv3_set_irq_type()
619 writel_relaxed(0, GICD + GICD_ICFGR + (i / 16) * 4); in gicv3_dist_init()
/xen/xen/include/asm-arm/
A Dgic.h47 #define GICD_ICFGR (0xC00) macro
/xen/xen/arch/arm/vgic/
A Dvgic-mmio-v2.c292 REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR,

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