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Searched refs:GICD_ICPENDR (Results 1 – 6 of 6) sorted by relevance

/xen/xen/arch/arm/
A Dvgic-v2.c245 case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN): in vgic_v2_distr_mmio_read()
480 case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN): in vgic_v2_distr_mmio_write()
484 v, r, gicd_reg - GICD_ICPENDR); in vgic_v2_distr_mmio_write()
A Dvgic-v3.c712 case VRANGE32(GICD_ICPENDR, GICD_ICPENDR): in __vgic_v3_distr_common_mmio_read()
816 case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN): in __vgic_v3_distr_common_mmio_write()
820 v, name, r, reg - GICD_ICPENDR); in __vgic_v3_distr_common_mmio_write()
1195 case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN): in vgic_v3_distr_mmio_read()
1382 case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN): in vgic_v3_distr_mmio_write()
A Dgic-v2.c290 gicv2_poke_irq(irqd, GICD_ICPENDR); in gicv2_set_pending_state()
A Dgic-v3.c523 gicv3_poke_irq(irqd, GICD_ICPENDR, false); in gicv3_set_pending_state()
/xen/xen/include/asm-arm/
A Dgic.h35 #define GICD_ICPENDR (0x280) macro
/xen/xen/arch/arm/vgic/
A Dvgic-mmio-v2.c277 REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICPENDR,

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