1 /* 2 * Copyright (C) 2007 Advanced Micro Devices, Inc. 3 * Author: Leo Duran <leo.duran@amd.com> 4 * Author: Wei Wang <wei.wang2@amd.com> - adapted to xen 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef AMD_IOMMU_DEFS_H 21 #define AMD_IOMMU_DEFS_H 22 23 /* IOMMU Command Buffer entries: in power of 2 increments, minimum of 256 */ 24 #define IOMMU_CMD_BUFFER_DEFAULT_ENTRIES 512 25 26 /* IOMMU Event Log entries: in power of 2 increments, minimum of 256 */ 27 #define IOMMU_EVENT_LOG_DEFAULT_ENTRIES 512 28 29 /* IOMMU PPR Log entries: in power of 2 increments, minimum of 256 */ 30 #define IOMMU_PPR_LOG_DEFAULT_ENTRIES 512 31 32 #define PTE_PER_TABLE_SHIFT 9 33 #define PTE_PER_TABLE_SIZE (1 << PTE_PER_TABLE_SHIFT) 34 #define PTE_PER_TABLE_MASK (~(PTE_PER_TABLE_SIZE - 1)) 35 #define PTE_PER_TABLE_ALIGN(entries) \ 36 (((entries) + PTE_PER_TABLE_SIZE - 1) & PTE_PER_TABLE_MASK) 37 #define PTE_PER_TABLE_ALLOC(entries) \ 38 PAGE_SIZE * (PTE_PER_TABLE_ALIGN(entries) >> PTE_PER_TABLE_SHIFT) 39 40 #define amd_offset_level_address(offset, level) \ 41 ((uint64_t)(offset) << (12 + (PTE_PER_TABLE_SHIFT * ((level) - 1)))) 42 43 /* IOMMU Capability */ 44 #define PCI_CAP_ID_MASK 0x000000FF 45 #define PCI_CAP_ID_SHIFT 0 46 #define PCI_CAP_NEXT_PTR_MASK 0x0000FF00 47 #define PCI_CAP_NEXT_PTR_SHIFT 8 48 #define PCI_CAP_TYPE_MASK 0x00070000 49 #define PCI_CAP_TYPE_SHIFT 16 50 #define PCI_CAP_REV_MASK 0x00F80000 51 #define PCI_CAP_REV_SHIFT 19 52 #define PCI_CAP_IOTLB_MASK 0x01000000 53 #define PCI_CAP_IOTLB_SHIFT 24 54 #define PCI_CAP_HT_TUNNEL_MASK 0x02000000 55 #define PCI_CAP_HT_TUNNEL_SHIFT 25 56 #define PCI_CAP_NP_CACHE_MASK 0x04000000 57 #define PCI_CAP_NP_CACHE_SHIFT 26 58 #define PCI_CAP_EFRSUP_SHIFT 27 59 #define PCI_CAP_RESET_MASK 0x80000000 60 #define PCI_CAP_RESET_SHIFT 31 61 62 #define PCI_CAP_TYPE_IOMMU 0x3 63 64 #define PCI_CAP_MMIO_BAR_LOW_OFFSET 0x04 65 #define PCI_CAP_MMIO_BAR_HIGH_OFFSET 0x08 66 #define PCI_CAP_MMIO_BAR_LOW_MASK 0xFFFFC000 67 #define IOMMU_MMIO_REGION_LENGTH 0x4000 68 69 #define PCI_CAP_RANGE_OFFSET 0x0C 70 #define PCI_CAP_BUS_NUMBER_MASK 0x0000FF00 71 #define PCI_CAP_BUS_NUMBER_SHIFT 8 72 #define PCI_CAP_FIRST_DEVICE_MASK 0x00FF0000 73 #define PCI_CAP_FIRST_DEVICE_SHIFT 16 74 #define PCI_CAP_LAST_DEVICE_MASK 0xFF000000 75 #define PCI_CAP_LAST_DEVICE_SHIFT 24 76 77 #define PCI_CAP_UNIT_ID_MASK 0x0000001F 78 #define PCI_CAP_UNIT_ID_SHIFT 0 79 #define PCI_CAP_MISC_INFO_OFFSET 0x10 80 #define PCI_CAP_MSI_NUMBER_MASK 0x0000001F 81 #define PCI_CAP_MSI_NUMBER_SHIFT 0 82 83 /* Device Table */ 84 #define IOMMU_DEV_TABLE_BASE_LOW_OFFSET 0x00 85 #define IOMMU_DEV_TABLE_BASE_HIGH_OFFSET 0x04 86 #define IOMMU_DEV_TABLE_SIZE_MASK 0x000001FF 87 #define IOMMU_DEV_TABLE_SIZE_SHIFT 0 88 89 #define IOMMU_DEV_TABLE_ENTRIES_PER_BUS 256 90 #define IOMMU_DEV_TABLE_ENTRY_SIZE 32 91 #define IOMMU_DEV_TABLE_U32_PER_ENTRY (IOMMU_DEV_TABLE_ENTRY_SIZE / 4) 92 93 #define IOMMU_DEV_TABLE_SYS_MGT_DMA_ABORTED 0x0 94 #define IOMMU_DEV_TABLE_SYS_MGT_MSG_FORWARDED 0x1 95 #define IOMMU_DEV_TABLE_SYS_MGT_INT_FORWARDED 0x2 96 #define IOMMU_DEV_TABLE_SYS_MGT_DMA_FORWARDED 0x3 97 98 #define IOMMU_DEV_TABLE_IO_CONTROL_ABORTED 0x0 99 #define IOMMU_DEV_TABLE_IO_CONTROL_FORWARDED 0x1 100 #define IOMMU_DEV_TABLE_IO_CONTROL_TRANSLATED 0x2 101 102 #define IOMMU_DEV_TABLE_INT_CONTROL_ABORTED 0x0 103 #define IOMMU_DEV_TABLE_INT_CONTROL_FORWARDED 0x1 104 #define IOMMU_DEV_TABLE_INT_CONTROL_TRANSLATED 0x2 105 106 struct amd_iommu_dte { 107 /* 0 - 63 */ 108 bool v:1; 109 bool tv:1; 110 unsigned int :5; 111 unsigned int had:2; 112 unsigned int paging_mode:3; 113 uint64_t pt_root:40; 114 bool ppr:1; 115 bool gprp:1; 116 bool giov:1; 117 bool gv:1; 118 unsigned int glx:2; 119 unsigned int gcr3_trp_14_12:3; 120 bool ir:1; 121 bool iw:1; 122 unsigned int :1; 123 124 /* 64 - 127 */ 125 unsigned int domain_id:16; 126 unsigned int gcr3_trp_30_15:16; 127 bool i:1; 128 bool se:1; 129 bool sa:1; 130 unsigned int ioctl:2; 131 bool cache:1; 132 bool sd:1; 133 bool ex:1; 134 unsigned int sys_mgt:2; 135 unsigned int :1; 136 unsigned int gcr3_trp_51_31:21; 137 138 /* 128 - 191 */ 139 bool iv:1; 140 unsigned int int_tab_len:4; 141 bool ig:1; 142 uint64_t it_root:46; 143 unsigned int :4; 144 bool init_pass:1; 145 bool ext_int_pass:1; 146 bool nmi_pass:1; 147 unsigned int :1; 148 unsigned int int_ctl:2; 149 bool lint0_pass:1; 150 bool lint1_pass:1; 151 152 /* 192 - 255 */ 153 uint64_t :54; 154 bool attr_v:1; 155 bool mode0_fc:1; 156 unsigned int snoop_attr:8; 157 }; 158 159 /* Command Buffer */ 160 #define IOMMU_CMD_BUFFER_BASE_LOW_OFFSET 0x08 161 #define IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET 0x0C 162 #define IOMMU_CMD_BUFFER_HEAD_OFFSET 0x2000 163 #define IOMMU_CMD_BUFFER_TAIL_OFFSET 0x2008 164 #define IOMMU_CMD_BUFFER_LENGTH_MASK 0x0F000000 165 #define IOMMU_CMD_BUFFER_LENGTH_SHIFT 24 166 167 #define IOMMU_CMD_BUFFER_ENTRY_SIZE 16 168 #define IOMMU_CMD_BUFFER_POWER_OF2_ENTRIES_PER_PAGE 8 169 170 #define IOMMU_CMD_OPCODE_MASK 0xF0000000 171 #define IOMMU_CMD_OPCODE_SHIFT 28 172 #define IOMMU_CMD_COMPLETION_WAIT 0x1 173 #define IOMMU_CMD_INVALIDATE_DEVTAB_ENTRY 0x2 174 #define IOMMU_CMD_INVALIDATE_IOMMU_PAGES 0x3 175 #define IOMMU_CMD_INVALIDATE_IOTLB_PAGES 0x4 176 #define IOMMU_CMD_INVALIDATE_INT_TABLE 0x5 177 #define IOMMU_CMD_COMPLETE_PPR_REQUEST 0x7 178 #define IOMMU_CMD_INVALIDATE_IOMMU_ALL 0x8 179 180 /* COMPLETION_WAIT command */ 181 #define IOMMU_COMP_WAIT_DATA_BUFFER_SIZE 8 182 #define IOMMU_COMP_WAIT_DATA_BUFFER_ALIGNMENT 8 183 #define IOMMU_COMP_WAIT_S_FLAG_MASK 0x00000001 184 #define IOMMU_COMP_WAIT_S_FLAG_SHIFT 0 185 #define IOMMU_COMP_WAIT_I_FLAG_MASK 0x00000002 186 #define IOMMU_COMP_WAIT_I_FLAG_SHIFT 1 187 #define IOMMU_COMP_WAIT_F_FLAG_MASK 0x00000004 188 #define IOMMU_COMP_WAIT_F_FLAG_SHIFT 2 189 #define IOMMU_COMP_WAIT_ADDR_LOW_MASK 0xFFFFFFF8 190 #define IOMMU_COMP_WAIT_ADDR_LOW_SHIFT 3 191 #define IOMMU_COMP_WAIT_ADDR_HIGH_MASK 0x000FFFFF 192 #define IOMMU_COMP_WAIT_ADDR_HIGH_SHIFT 0 193 194 /* INVALIDATE_IOMMU_PAGES command */ 195 #define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_MASK 0x0000FFFF 196 #define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_SHIFT 0 197 #define IOMMU_INV_IOMMU_PAGES_S_FLAG_MASK 0x00000001 198 #define IOMMU_INV_IOMMU_PAGES_S_FLAG_SHIFT 0 199 #define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_MASK 0x00000002 200 #define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_SHIFT 1 201 #define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_MASK 0xFFFFF000 202 #define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_SHIFT 12 203 #define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_MASK 0xFFFFFFFF 204 #define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_SHIFT 0 205 206 /* INVALIDATE_DEVTAB_ENTRY command */ 207 #define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_MASK 0x0000FFFF 208 #define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_SHIFT 0 209 210 /* INVALIDATE_INTERRUPT_TABLE command */ 211 #define IOMMU_INV_INT_TABLE_DEVICE_ID_MASK 0x0000FFFF 212 #define IOMMU_INV_INT_TABLE_DEVICE_ID_SHIFT 0 213 214 /* INVALIDATE_IOTLB_PAGES command */ 215 #define IOMMU_INV_IOTLB_PAGES_MAXPEND_MASK 0xff000000 216 #define IOMMU_INV_IOTLB_PAGES_MAXPEND_SHIFT 24 217 #define IOMMU_INV_IOTLB_PAGES_PASID1_MASK 0x00ff0000 218 #define IOMMU_INV_IOTLB_PAGES_PASID1_SHIFT 16 219 #define IOMMU_INV_IOTLB_PAGES_PASID2_MASK 0x0fff0000 220 #define IOMMU_INV_IOTLB_PAGES_PASID2_SHIFT 16 221 #define IOMMU_INV_IOTLB_PAGES_QUEUEID_MASK 0x0000ffff 222 #define IOMMU_INV_IOTLB_PAGES_QUEUEID_SHIFT 0 223 #define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_MASK 0x0000FFFF 224 #define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_SHIFT 0 225 #define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_MASK 0xFFFFF000 226 #define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_SHIFT 12 227 #define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_MASK 0xFFFFFFFF 228 #define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_SHIFT 0 229 #define IOMMU_INV_IOTLB_PAGES_S_FLAG_MASK 0x00000001 230 #define IOMMU_INV_IOTLB_PAGES_S_FLAG_SHIFT 0 231 232 /* Event Log */ 233 #define IOMMU_EVENT_LOG_BASE_LOW_OFFSET 0x10 234 #define IOMMU_EVENT_LOG_BASE_HIGH_OFFSET 0x14 235 #define IOMMU_EVENT_LOG_HEAD_OFFSET 0x2010 236 #define IOMMU_EVENT_LOG_TAIL_OFFSET 0x2018 237 #define IOMMU_EVENT_LOG_LENGTH_MASK 0x0F000000 238 #define IOMMU_EVENT_LOG_LENGTH_SHIFT 24 239 #define IOMMU_EVENT_LOG_HEAD_MASK 0x0007FFF0 240 #define IOMMU_EVENT_LOG_HEAD_SHIFT 4 241 #define IOMMU_EVENT_LOG_TAIL_MASK 0x0007FFF0 242 #define IOMMU_EVENT_LOG_TAIL_SHIFT 4 243 244 #define IOMMU_EVENT_LOG_ENTRY_SIZE 16 245 #define IOMMU_EVENT_LOG_POWER_OF2_ENTRIES_PER_PAGE 8 246 #define IOMMU_EVENT_LOG_U32_PER_ENTRY (IOMMU_EVENT_LOG_ENTRY_SIZE / 4) 247 248 #define IOMMU_EVENT_CODE_MASK 0xF0000000 249 #define IOMMU_EVENT_CODE_SHIFT 28 250 #define IOMMU_EVENT_ILLEGAL_DEV_TABLE_ENTRY 0x1 251 #define IOMMU_EVENT_IO_PAGE_FAULT 0x2 252 #define IOMMU_EVENT_DEV_TABLE_HW_ERROR 0x3 253 #define IOMMU_EVENT_PAGE_TABLE_HW_ERROR 0x4 254 #define IOMMU_EVENT_ILLEGAL_COMMAND_ERROR 0x5 255 #define IOMMU_EVENT_COMMAND_HW_ERROR 0x6 256 #define IOMMU_EVENT_IOTLB_INV_TIMEOUT 0x7 257 #define IOMMU_EVENT_INVALID_DEV_REQUEST 0x8 258 259 #define IOMMU_EVENT_DOMAIN_ID_MASK 0x0000FFFF 260 #define IOMMU_EVENT_DOMAIN_ID_SHIFT 0 261 #define IOMMU_EVENT_DEVICE_ID_MASK 0x0000FFFF 262 #define IOMMU_EVENT_DEVICE_ID_SHIFT 0 263 #define IOMMU_EVENT_FLAGS_SHIFT 16 264 #define IOMMU_EVENT_FLAGS_MASK 0x0FFF0000 265 266 /* PPR Log */ 267 #define IOMMU_PPR_LOG_ENTRY_SIZE 16 268 #define IOMMU_PPR_LOG_POWER_OF2_ENTRIES_PER_PAGE 8 269 #define IOMMU_PPR_LOG_U32_PER_ENTRY (IOMMU_PPR_LOG_ENTRY_SIZE / 4) 270 271 #define IOMMU_PPR_LOG_BASE_LOW_OFFSET 0x0038 272 #define IOMMU_PPR_LOG_BASE_HIGH_OFFSET 0x003C 273 #define IOMMU_PPR_LOG_BASE_LOW_MASK 0xFFFFF000 274 #define IOMMU_PPR_LOG_BASE_LOW_SHIFT 12 275 #define IOMMU_PPR_LOG_BASE_HIGH_MASK 0x000FFFFF 276 #define IOMMU_PPR_LOG_BASE_HIGH_SHIFT 0 277 #define IOMMU_PPR_LOG_LENGTH_MASK 0x0F000000 278 #define IOMMU_PPR_LOG_LENGTH_SHIFT 24 279 #define IOMMU_PPR_LOG_HEAD_MASK 0x0007FFF0 280 #define IOMMU_PPR_LOG_HEAD_SHIFT 4 281 #define IOMMU_PPR_LOG_TAIL_MASK 0x0007FFF0 282 #define IOMMU_PPR_LOG_TAIL_SHIFT 4 283 #define IOMMU_PPR_LOG_HEAD_OFFSET 0x2030 284 #define IOMMU_PPR_LOG_TAIL_OFFSET 0x2038 285 #define IOMMU_PPR_LOG_DEVICE_ID_MASK 0x0000FFFF 286 #define IOMMU_PPR_LOG_DEVICE_ID_SHIFT 0 287 #define IOMMU_PPR_LOG_CODE_MASK 0xF0000000 288 #define IOMMU_PPR_LOG_CODE_SHIFT 28 289 290 #define IOMMU_LOG_ENTRY_TIMEOUT 1000 291 292 /* Control Register */ 293 #define IOMMU_CONTROL_MMIO_OFFSET 0x18 294 295 union amd_iommu_control { 296 uint64_t raw; 297 struct { 298 bool iommu_en:1; 299 bool ht_tun_en:1; 300 bool event_log_en:1; 301 bool event_int_en:1; 302 bool com_wait_int_en:1; 303 unsigned int inv_timeout:3; 304 bool pass_pw:1; 305 bool res_pass_pw:1; 306 bool coherent:1; 307 bool isoc:1; 308 bool cmd_buf_en:1; 309 bool ppr_log_en:1; 310 bool ppr_int_en:1; 311 bool ppr_en:1; 312 bool gt_en:1; 313 bool ga_en:1; 314 unsigned int crw:4; 315 bool smif_en:1; 316 bool slf_wb_dis:1; 317 bool smif_log_en:1; 318 unsigned int gam_en:3; 319 bool ga_log_en:1; 320 bool ga_int_en:1; 321 unsigned int dual_ppr_log_en:2; 322 unsigned int dual_event_log_en:2; 323 unsigned int dev_tbl_seg_en:3; 324 unsigned int priv_abrt_en:2; 325 bool ppr_auto_rsp_en:1; 326 bool marc_en:1; 327 bool blk_stop_mrk_en:1; 328 bool ppr_auto_rsp_aon:1; 329 bool domain_id_pne:1; 330 unsigned int :1; 331 bool eph_en:1; 332 unsigned int had_update:2; 333 bool gd_update_dis:1; 334 unsigned int :1; 335 bool xt_en:1; 336 bool int_cap_xt_en:1; 337 bool vcmd_en:1; 338 bool viommu_en:1; 339 bool ga_update_dis:1; 340 bool gappi_en:1; 341 unsigned int :8; 342 }; 343 }; 344 345 /* Exclusion Register */ 346 #define IOMMU_EXCLUSION_BASE_LOW_OFFSET 0x20 347 #define IOMMU_EXCLUSION_BASE_HIGH_OFFSET 0x24 348 #define IOMMU_EXCLUSION_LIMIT_LOW_OFFSET 0x28 349 #define IOMMU_EXCLUSION_LIMIT_HIGH_OFFSET 0x2C 350 #define IOMMU_EXCLUSION_BASE_LOW_MASK 0xFFFFF000 351 #define IOMMU_EXCLUSION_BASE_LOW_SHIFT 12 352 #define IOMMU_EXCLUSION_BASE_HIGH_MASK 0xFFFFFFFF 353 #define IOMMU_EXCLUSION_BASE_HIGH_SHIFT 0 354 #define IOMMU_EXCLUSION_RANGE_ENABLE_MASK 0x00000001 355 #define IOMMU_EXCLUSION_RANGE_ENABLE_SHIFT 0 356 #define IOMMU_EXCLUSION_ALLOW_ALL_MASK 0x00000002 357 #define IOMMU_EXCLUSION_ALLOW_ALL_SHIFT 1 358 #define IOMMU_EXCLUSION_LIMIT_LOW_MASK 0xFFFFF000 359 #define IOMMU_EXCLUSION_LIMIT_LOW_SHIFT 12 360 #define IOMMU_EXCLUSION_LIMIT_HIGH_MASK 0xFFFFFFFF 361 #define IOMMU_EXCLUSION_LIMIT_HIGH_SHIFT 0 362 363 /* Extended Feature Register */ 364 #define IOMMU_EXT_FEATURE_MMIO_OFFSET 0x30 365 366 union amd_iommu_ext_features { 367 uint64_t raw; 368 struct { 369 unsigned int pref_sup:1; 370 unsigned int ppr_sup:1; 371 unsigned int xt_sup:1; 372 unsigned int nx_sup:1; 373 unsigned int gt_sup:1; 374 unsigned int gappi_sup:1; 375 unsigned int ia_sup:1; 376 unsigned int ga_sup:1; 377 unsigned int he_sup:1; 378 unsigned int pc_sup:1; 379 unsigned int hats:2; 380 unsigned int gats:2; 381 unsigned int glx_sup:2; 382 unsigned int smif_sup:2; 383 unsigned int smif_rc:3; 384 unsigned int gam_sup:3; 385 unsigned int dual_ppr_log_sup:2; 386 unsigned int :2; 387 unsigned int dual_event_log_sup:2; 388 unsigned int :1; 389 unsigned int sats_sup:1; 390 unsigned int pas_max:5; 391 unsigned int us_sup:1; 392 unsigned int dev_tbl_seg_sup:2; 393 unsigned int ppr_early_of_sup:1; 394 unsigned int ppr_auto_rsp_sup:1; 395 unsigned int marc_sup:2; 396 unsigned int blk_stop_mrk_sup:1; 397 unsigned int perf_opt_sup:1; 398 unsigned int msi_cap_mmio_sup:1; 399 unsigned int :1; 400 unsigned int gio_sup:1; 401 unsigned int ha_sup:1; 402 unsigned int eph_sup:1; 403 unsigned int attr_fw_sup:1; 404 unsigned int hd_sup:1; 405 unsigned int :1; 406 unsigned int inv_iotlb_type_sup:1; 407 unsigned int viommu_sup:1; 408 unsigned int vm_guard_io_sup:1; 409 unsigned int vm_table_size:4; 410 unsigned int ga_update_dis_sup:1; 411 unsigned int :2; 412 } flds; 413 }; 414 415 /* x2APIC Control Registers */ 416 #define IOMMU_XT_INT_CTRL_MMIO_OFFSET 0x0170 417 #define IOMMU_XT_PPR_INT_CTRL_MMIO_OFFSET 0x0178 418 #define IOMMU_XT_GA_INT_CTRL_MMIO_OFFSET 0x0180 419 420 union amd_iommu_x2apic_control { 421 uint64_t raw; 422 struct { 423 unsigned int :2; 424 unsigned int dest_mode:1; 425 unsigned int :5; 426 unsigned int dest_lo:24; 427 unsigned int vector:8; 428 unsigned int int_type:1; /* DM in IOMMU spec 3.04 */ 429 unsigned int :15; 430 unsigned int dest_hi:8; 431 }; 432 }; 433 434 /* Status Register*/ 435 #define IOMMU_STATUS_MMIO_OFFSET 0x2020 436 437 #define IOMMU_STATUS_EVENT_LOG_OVERFLOW 0x00000001 438 #define IOMMU_STATUS_EVENT_LOG_INT 0x00000002 439 #define IOMMU_STATUS_COMP_WAIT_INT 0x00000004 440 #define IOMMU_STATUS_EVENT_LOG_RUN 0x00000008 441 #define IOMMU_STATUS_CMD_BUFFER_RUN 0x00000010 442 #define IOMMU_STATUS_PPR_LOG_OVERFLOW 0x00000020 443 #define IOMMU_STATUS_PPR_LOG_INT 0x00000040 444 #define IOMMU_STATUS_PPR_LOG_RUN 0x00000080 445 #define IOMMU_STATUS_GAPIC_LOG_OVERFLOW 0x00000100 446 #define IOMMU_STATUS_GAPIC_LOG_INT 0x00000200 447 #define IOMMU_STATUS_GAPIC_LOG_RUN 0x00000400 448 449 /* I/O Page Table */ 450 #define IOMMU_PAGE_TABLE_ENTRY_SIZE 8 451 #define IOMMU_PAGE_TABLE_U32_PER_ENTRY (IOMMU_PAGE_TABLE_ENTRY_SIZE / 4) 452 #define IOMMU_PAGE_TABLE_ALIGNMENT 4096 453 454 union amd_iommu_pte { 455 uint64_t raw; 456 struct { 457 bool pr:1; 458 unsigned int ign0:4; 459 bool a:1; 460 bool d:1; 461 unsigned int ign1:2; 462 unsigned int next_level:3; 463 uint64_t mfn:40; 464 unsigned int :7; 465 bool u:1; 466 bool fc:1; 467 bool ir:1; 468 bool iw:1; 469 unsigned int ign2:1; 470 }; 471 }; 472 473 /* Paging modes */ 474 #define IOMMU_PAGING_MODE_DISABLED 0x0 475 476 /* Flags */ 477 #define IOMMU_CONTROL_DISABLED 0 478 #define IOMMU_CONTROL_ENABLED 1 479 480 #define INV_IOMMU_ALL_PAGES_ADDRESS ((1ULL << 63) - 1) 481 482 #define IOMMU_RING_BUFFER_PTR_MASK 0x0007FFF0 483 484 #define IOMMU_CMD_DEVICE_ID_MASK 0x0000FFFF 485 #define IOMMU_CMD_DEVICE_ID_SHIFT 0 486 487 #define IOMMU_REG_BASE_ADDR_LOW_MASK 0xFFFFF000 488 #define IOMMU_REG_BASE_ADDR_LOW_SHIFT 12 489 #define IOMMU_REG_BASE_ADDR_HIGH_MASK 0x000FFFFF 490 #define IOMMU_REG_BASE_ADDR_HIGH_SHIFT 0 491 492 #endif /* AMD_IOMMU_DEFS_H */ 493 494 /* 495 * Local variables: 496 * mode: C 497 * c-file-style: "BSD" 498 * c-basic-offset: 4 499 * tab-width: 4 500 * indent-tabs-mode: nil 501 * End: 502 */ 503