Searched refs:PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET (Results 1 – 4 of 4) sorted by relevance
232 if ( offset != PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET ) in msixtbl_read()245 offset = PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; in msixtbl_read()252 if ( offset == PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET ) in msixtbl_read()296 if ( offset != PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET ) in msixtbl_write()385 BUILD_BUG_ON(!(PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET & 4)); in msixtbl_range()391 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET) && in msixtbl_range()409 BUILD_BUG_ON((PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET + 4) & in msixtbl_range()521 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET) ) in msixtbl_pt_register()
261 case PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET: in msix_read()351 case PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET: in msix_write()
362 writel(flag, entry->mask_base + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); in msi_set_mask_bit()363 readl(entry->mask_base + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); in msi_set_mask_bit()417 return readl(entry->mask_base + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET) & 1; in msi_get_mask_bit()917 writel(1, base + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); in msix_capability_init()1134 writel(1, entry->mask_base + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); in __pci_disable_msix()
321 #define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12 macro
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