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Searched refs:R (Results 1 – 25 of 32) sorted by relevance

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/xen/tools/tests/x86_emulator/
A Dpredicates.c13 #define R mem_read macro
55 { { 0x02 }, { 2, 2 }, T, R }, /* add */
56 { { 0x03 }, { 2, 2 }, T, R }, /* add */
63 { { 0x0a }, { 2, 2 }, T, R }, /* or */
64 { { 0x0b }, { 2, 2 }, T, R }, /* or */
70 { { 0x12 }, { 2, 2 }, T, R }, /* adc */
71 { { 0x13 }, { 2, 2 }, T, R }, /* adc */
78 { { 0x1a }, { 2, 2 }, T, R }, /* adc */
79 { { 0x1b }, { 2, 2 }, T, R }, /* adc */
86 { { 0x22 }, { 2, 2 }, T, R }, /* and */
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A Dopmask.S2 # define R(x) e##x macro
6 # define R(x) r##x macro
8 # define R(x) e##x macro
35 _(kmov) %\res2, %R(dx)
36 cmp DATA(out), %R(dx)
58 mov DATA(in2), %R(ax)
59 _(kmov) %R(ax), %k2
A Dblowfish.c434 uint32_t L = input >> 32, R = input; in blowfish_test() local
437 Blowfish_Encrypt(&ctx, &L, &R); in blowfish_test()
438 Blowfish_Decrypt(&ctx, &L, &R); in blowfish_test()
439 return ((uint64_t)L << 32) | R; in blowfish_test()
/xen/xen/include/asm-arm/arm32/
A Dsysregs.h56 #define READ_SYSREG32(R...) READ_CP32(R) argument
57 #define WRITE_SYSREG32(V, R...) WRITE_CP32(V, R) argument
59 #define READ_SYSREG64(R...) READ_CP64(R) argument
60 #define WRITE_SYSREG64(V, R...) WRITE_CP64(V, R) argument
62 #define READ_SYSREG(R...) READ_SYSREG32(R) argument
63 #define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) argument
A Dpage.h23 #define __invalidate_dcache_one(R) STORE_CP32(R, DCIMVAC) argument
26 #define __clean_dcache_one(R) STORE_CP32(R, DCCMVAC) argument
30 #define __clean_and_invalidate_dcache_one(R) STORE_CP32(R, DCCIMVAC) argument
/xen/xen/include/asm-arm/arm64/
A Dpage.h20 #define __invalidate_dcache_one(R) "dc ivac, %" #R ";" argument
23 #define __clean_dcache_one(R) \ argument
24 ALTERNATIVE("dc cvac, %" #R ";", \
25 "dc civac, %" #R ";", \
30 #define __clean_and_invalidate_dcache_one(R) "dc civac, %" #R ";" argument
/xen/tools/tests/mem-sharing/
A Dmemshrtool.c37 #define R(f) do { \ macro
83 R(xc_memshr_control(xch, domid, 1)); in main()
93 R(xc_memshr_control(xch, domid, 0)); in main()
106 R(xc_memshr_nominate_gfn(xch, domid, gfn, &handle)); in main()
127 R(xc_memshr_share_gfns(xch, source_domid, source_gfn, source_handle, domid, gfn, handle)); in main()
143 R((int)!map); in main()
161 R(xc_memshr_add_to_physmap(xch, source_domid, source_gfn, source_handle, domid, gfn)); in main()
173 R(xc_memshr_debug_gfn(xch, domid, gfn)); in main()
/xen/tools/firmware/vgabios/
A Dvbe_display_api.txt131 * VBE_DISPI_INDEX_ID : WORD {R,W}
141 * VBE_DISPI_INDEX_XRES : WORD {R,W}
149 * VBE_DISPI_INDEX_YRES : WORD {R,W}
157 * VBE_DISPI_INDEX_BPP : WORD {R,W}
165 * VBE_DISPI_INDEX_ENABLE : WORD {R,W}
173 * VBE_DISPI_INDEX_BANK : WORD {R,W}
188 * VBE_DISPI_INDEX_X_OFFSET : WORD {R,W}
192 * VBE_DISPI_INDEX_Y_OFFSET : WORD {R,W}
198 * VBE_DISPI_INDEX_BPP : WORD {R,W}
202 * VBE_DISPI_INDEX_ENABLE : WORD {R,W}
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/xen/xen/drivers/passthrough/
A DKconfig17 bool "Renesas IPMMU-VMSA found in R-Car Gen3 SoCs" if EXPERT
21 in R-Car Gen3 SoCs.
23 Say Y here if you are using newest R-Car Gen3 SoCs revisions
/xen/xen/drivers/char/
A DKconfig36 This selects the ARM(R) AMBA(R) PrimeCell PL011 UART. If you have
61 or Renesas R-Car Gen 2/3 based board say Y.
/xen/docs/designs/
A Dargo.pandoc229 To take `rings_L2` you must already have `R(L1)`. `W(L1)` implies `W(rings_L2)`
234 * `R(L1_global_argo_rwlock)` must be acquired before taking either read or
299 `[entry] > -- [ take R(L1) ] -- [ take R(L2) ] -- loop [ take a L3 / drop L3 ]
300 -- [ drop R(L2) ] -- [ drop R(L1)] -- > [exit]`
317 eg. On entry to logic that requires holding at least `R(rings_L2)`, this:
324 `R(rings_L2) && R(L1)`
325 or: `W(rings_L2) && R(L1)`
345 * definition because the first clause that is testing R(L1) && R(L2) will also
346 * return true if R(L1) && W(L2) is true, because of the way that rw_is_locked
392 because _at least_ `R(rings_L2)` is already held, as documented and verified by
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/xen/
A DMAINTAINERS65 R: Designated reviewer: FullName <address@domain>
234 R: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
304 INTEL(R) TRUSTED EXECUTION TECHNOLOGY (TXT)
310 INTEL(R) VT FOR DIRECTED I/O (VT-D)
315 INTEL(R) VT FOR X86 (VT-X)
377 R: Wei Liu <wl@xen.org>
485 R: Alexandru Isaila <aisaila@bitdefender.com>
486 R: Petre Pircalabu <ppircalabu@bitdefender.com>
523 R: Wei Liu <wl@xen.org>
524 R: Roger Pau Monné <roger.pau@citrix.com>
[all …]
A DREADME191 Intel(R) Trusted Execution Technology Support
194 Intel's technology for safer computing, Intel(R) Trusted Execution Technology
195 (Intel(R) TXT), defines platform-level enhancements that provide the building
199 Intel(R) TXT support is provided by the Trusted Boot (tboot) module in
202 Tboot is an open source, pre- kernel/VMM module that uses Intel(R) TXT to
A Dconfig.guess1278 R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*)
1315 SX-8R:SUPER-UX:*:*)
/xen/docs/man/
A Dxenstore-read.1.pod23 =item B<-R>
A Dxenstore-write.1.pod20 =item B<-R>
A Dxentop.1.pod80 =item B<R>
/xen/tools/ocaml/xenstored/
A Dsystemd.ml2 * Copyright (C) 2014 Luis R. Rodriguez <mcgrof@suse.com>
A Dsystemd.mli2 * Copyright (C) 2014 Luis R. Rodriguez <mcgrof@suse.com>
/xen/m4/
A DREADME.source40 systemd.m4 was contributed to by Luis R. Rodriguez <mcgrof@do-not-panic.com>,
A Dsystemd.m43 # Copyright (C) 2014 Luis R. Rodriguez <mcgrof@suse.com>
/xen/xen/tools/
A Dxen.flf1888 0x0154 LATIN CAPITAL LETTER R WITH ACUTE
1895 0x0155 LATIN SMALL LETTER R WITH ACUTE
1902 0x0156 LATIN CAPITAL LETTER R WITH CEDILLA
1909 0x0157 LATIN SMALL LETTER R WITH CEDILLA
1916 0x0158 LATIN CAPITAL LETTER R WITH CARON
1923 0x0159 LATIN SMALL LETTER R WITH CARON
/xen/docs/admin-guide/
A Dmicrocode-loading.rst50 model name : Intel(R) Xeon(R) CPU E3-1240 v3 @ 3.40GHz
/xen/xen/arch/arm/
A DKconfig.debug136 bool "Early printk with SCIF0 on Renesas Lager board (R-Car H2 processor)"
149 bool "Early printk with SCIF2 on Renesas R-Car Gen3 processors"
/xen/tools/xentrace/
A Dxenalyze.c1974 int I, J, L, R, K; in percentile() local
1986 L=0; R=N-1; in percentile()
1988 while(L < R) { in percentile()
1994 J=R; in percentile()
2020 R=J; in percentile()
2052 R=N-1; in weighted_percentile()
2056 while(L < R) { in weighted_percentile()
2104 R=J; in weighted_percentile()
2139 R=N-1; in self_weighted_percentile()
2143 while(L < R) { in self_weighted_percentile()
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