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Searched refs:TLBIMVAHIS (Results 1 – 2 of 2) sorted by relevance

/xen/xen/include/asm-arm/arm32/
A Dflushtlb.h52 asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory"); in __flush_xen_tlb_one()
/xen/xen/include/asm-arm/
A Dcpregs.h215 #define TLBIMVAHIS p15,4,c8,c3,1 /* Invalidate Unified Hyp. TLB by MVA inner shareable */ macro

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