Searched refs:apic_base_msr (Results 1 – 5 of 5) sorted by relevance
51 ((vlapic)->hw.apic_base_msr & APIC_BASE_ADDR_MASK)54 ((vlapic)->hw.apic_base_msr & APIC_BASE_EXTD)57 !((vlapic)->hw.apic_base_msr & APIC_BASE_EXTD))
1141 if ( (vlapic->hw.apic_base_msr ^ value) & APIC_BASE_ENABLE ) in guest_wrmsr_apic_base()1158 else if ( ((vlapic->hw.apic_base_msr ^ value) & APIC_BASE_EXTD) && in guest_wrmsr_apic_base()1162 vlapic->hw.apic_base_msr = value; in guest_wrmsr_apic_base()1171 "apic base msr is 0x%016"PRIx64, vlapic->hw.apic_base_msr); in guest_wrmsr_apic_base()1443 vlapic->hw.apic_base_msr = APIC_BASE_ENABLE | APIC_DEFAULT_PHYS_BASE; in vlapic_reset()1445 vlapic->hw.apic_base_msr |= APIC_BASE_BSP; in vlapic_reset()1553 if ( !(s->hw.apic_base_msr & APIC_BASE_ENABLE) && in lapic_load_hidden()
3498 *msr_content = vcpu_vlapic(v)->hw.apic_base_msr; in hvm_msr_read_intercept()
410 uint64_t apic_base_msr; member
242 (unsigned long long) p.apic_base_msr, p.disabled, p.timer_divisor); in dump_lapic()
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