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Searched refs:c2 (Results 1 – 12 of 12) sorted by relevance

/xen/xen/include/asm-arm/
A Dcpregs.h117 #define ID_ISAR0 p15,0,c0,c2,0 /* ISA Feature Register 0 */
118 #define ID_ISAR1 p15,0,c0,c2,1 /* ISA Feature Register 1 */
119 #define ID_ISAR2 p15,0,c0,c2,2 /* ISA Feature Register 2 */
120 #define ID_ISAR3 p15,0,c0,c2,3 /* ISA Feature Register 3 */
121 #define ID_ISAR4 p15,0,c0,c2,4 /* ISA Feature Register 4 */
122 #define ID_ISAR5 p15,0,c0,c2,5 /* ISA Feature Register 5 */
147 #define TTBR0_32 p15,0,c2,c0,0 /* 32-bit access to TTBR0 */
148 #define TTBR1_32 p15,0,c2,c0,1 /* 32-bit access to TTBR1 */
163 #define HSR p15,4,c5,c2,0 /* Hyp. Syndrome Register */
267 #define CNTP_TVAL p15,0,c14,c2,0 /* Physical Timer value */
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/xen/xen/common/
A Dstring.c21 unsigned char c1, c2; in strnicmp() local
23 c1 = 0; c2 = 0; in strnicmp()
26 c1 = *s1; c2 = *s2; in strnicmp()
30 if (!c2) in strnicmp()
32 if (c1 == c2) in strnicmp()
35 c2 = tolower(c2); in strnicmp()
36 if (c1 != c2) in strnicmp()
40 return (int)c1 - (int)c2; in strnicmp()
47 int c1, c2; variable
52 c2 = tolower(*s2++);
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/xen/xen/xsm/flask/ss/
A Dcontext.h84 static inline int mls_context_cmp(struct context *c1, struct context *c2) in mls_context_cmp() argument
89 return ((c1->range.level[0].sens == c2->range.level[0].sens) && in mls_context_cmp()
90 ebitmap_cmp(&c1->range.level[0].cat,&c2->range.level[0].cat) && in mls_context_cmp()
91 (c1->range.level[1].sens == c2->range.level[1].sens) && in mls_context_cmp()
92 ebitmap_cmp(&c1->range.level[1].cat,&c2->range.level[1].cat)); in mls_context_cmp()
124 static inline int context_cmp(struct context *c1, struct context *c2) in context_cmp() argument
126 return ((c1->user == c2->user) && in context_cmp()
127 (c1->role == c2->role) && in context_cmp()
128 (c1->type == c2->type) && in context_cmp()
129 mls_context_cmp(c1, c2)); in context_cmp()
/xen/xen/include/asm-arm/arm64/
A Dhsr.h43 #define HSR_SYSREG_MDSCR_EL1 HSR_SYSREG(2,0,c0,c2,2)
75 #define HSR_SYSREG_TTBR0_EL1 HSR_SYSREG(3,0,c2, c0,0)
76 #define HSR_SYSREG_TTBR1_EL1 HSR_SYSREG(3,0,c2, c0,1)
77 #define HSR_SYSREG_TCR_EL1 HSR_SYSREG(3,0,c2, c0,2)
80 #define HSR_SYSREG_ESR_EL1 HSR_SYSREG(3,0,c5, c2,0)
84 #define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0)
109 #define HSR_SYSREG_CNTP_TVAL_EL0 HSR_SYSREG(3,3,c14,c2,0)
110 #define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1)
111 #define HSR_SYSREG_CNTP_CVAL_EL0 HSR_SYSREG(3,3,c14,c2,2)
/xen/tools/libfsimage/iso9660/
A Diso9660.h211 #define RRMAGIC(c1, c2) ((c1)|(c2) << 8) argument
213 #define CHECK2(ptr, c1, c2) \ argument
214 (*(unsigned short *)(ptr) == (((c1) | (c2) << 8) & 0xFFFF))
/xen/tools/debugger/gdbsx/gx/
A Dgx_comm.c190 unsigned char csum, c1, c2; in gx_getpkt() local
220 c2 = gx_fromhex(readchar()); in gx_getpkt()
222 if (csum == (c1 << 4) + c2) in gx_getpkt()
226 (c1 << 4) + c2, csum, buf); in gx_getpkt()
/xen/xen/arch/x86/boot/
A Dcmdline.c71 unsigned char c1, c2; in strncmp() local
76 c2 = *ct++; in strncmp()
77 if ( c1 != c2 ) in strncmp()
78 return c1 < c2 ? -1 : 1; in strncmp()
/xen/tools/ocaml/xenstored/
A Dperms.ml121 | c1, Some c2 -> [ fst c1; fst c2 ]
/xen/tools/libxl/
A Dlibxl_dom.c133 const libxl__numa_candidate *c2) in numa_cmpf() argument
135 if (c1->nr_vcpus != c2->nr_vcpus) in numa_cmpf()
136 return c1->nr_vcpus - c2->nr_vcpus; in numa_cmpf()
138 return c2->free_memkb - c1->free_memkb; in numa_cmpf()
A Dlibxl_internal.h4457 const libxl__numa_candidate *c2);
/xen/
A Dconfig.guess792 else echo c2-convex-bsd
/xen/tools/tests/x86_emulator/
A Devex-disp8.c111 INSN_FP(cmp, 0f, c2),

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